ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Glossary
Exception
Handles an event. For example, an exception could handle an external interrupt or an Undefined Instruction.
Exception modes
Are privileged modes that are entered when specific exceptions occur.
Exception vector
Is one of a number of fixed addresses in low memory, or in high memory if high vectors are configured.
Execution stream
The stream of instructions that would have been executed by sequential execution of the program.
Explicit access
A read from memory, or a write to memory, generated by a load/store instruction executed in the processor.
Reads and writes generated by L1 DMA accesses or hardware translation table accesses are not explicit
accesses.
External abort
Is an abort that is generated by the external memory system.
Fault Is an abort that is generated by the MMU.
Fast Context Switch Extension (FCSE)
Modifies the behavior of an ARM memory system to enable multiple programs running on the ARM
processor to use identical address ranges, while ensuring that the addresses they present to the rest of the
memory system differ. From ARMv6, use of the FCSE is deprecated, and the FCSE is optional in ARMv7.
FCSE See Fast Context Switch Extension.
Flat address mapping
Is where the physical address for every access is equal to its virtual address.
Flush-to-zero mode
Is a special processing mode that optimizes the performance of some VFP algorithms by replacing the
denormalized operands and intermediate results with zeros, without significantly affecting the accuracy of
their final results.
Fully-associative cache
Has just one cache set, that consists of the entire cache. See also direct-mapped cache.
General-purpose register
Is one of the 32-bit general-purpose integer registers, R0 to R15. Note that R15 holds the Program Counter,
and there are often limitations on its use that do not apply to R0 to R14.
Halfword
Is a 16-bit data item. Halfwords are normally halfword-aligned in ARM systems.
Halfword-aligned
Means that the address is divisible by 2.
High registers
Are ARM core registers 8 to 15, that can be accessed by some Thumb instructions.
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