ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Common Memory System Architecture Features
The invalidate MVA from branch predictor array operation operates on the address of the branch instruction.
It includes the current system ASID and the security state when determining which line is affected as part
of any required VA to PA translation. Security state checking is performed only if the Security Extensions
are implemented. The invalidate by MVA operation can affect other branch predictor entries.
Note
The architecture does not make visible the range of addresses in a branch predictor to which the invalidate
operation applies. This means the address used in the invalidate MVA instruction must be the address of the
branch to be invalidated.
If the correct functioning of a system requires invalidation of the branch predictor when there are changes
to the instructions in memory, the invalidate entire instruction cache operation also causes an invalidate
entire branch predictor array operation.
Branch predictor maintenance operations and the memory order model
The following rule describes the effect of the memory order model on the branch predictor maintenance
operations:
Any invalidation of the branch predictor is guaranteed to take effect only after one of the following:
— execution of a ISB instruction
— taking an exception
— return from an exception.
Therefore, if a branch instruction appears between an invalidate branch prediction instruction and an ISB
operation, exception entry or exception return, it is UNPREDICTABLE whether the branch instruction is
affected by the invalidate. Software must avoid this ordering of instructions, because it might lead to
UNPREDICTABLE behavior.
The branch predictor maintenance operations must be used to invalidate entries in the branch predictor after
any of the following events:
enabling or disabling the MMU
writing new data to instruction locations
writing new mappings to the translation tables
changes to the TTBR0, TTBR1, or TTBCR registers, unless accompanied by a change to the
ContextID or the FCSE ProcessID.
Failure to invalidate entries might give UNPREDICTABLE results, caused by the execution of old branches.
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