ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
External abort on instruction fetch
An external abort on an instruction fetch can be either synchronous or asynchronous. A synchronous
external abort on an instruction fetch is taken precisely.
An implementation can report the external abort asynchronously from the instruction that it applies to. In
such an implementation these aborts behave essentially as interrupts. They are masked by the CPSR.A bit
when it is set to 1, otherwise they are reported using the Data Abort exception.
External abort on data read or write
Externally generated errors during a data read or write can be either synchronous or asynchronous.
An implementation can report the external abort asynchronously from the instruction that generated the
access. In such an implementation these aborts behave essentially as interrupts. They are masked by the
CPSR.A bit when it is set to 1, otherwise they are reported using the Data Abort exception.
External abort on a translation table walk
An external abort on a translation table walk can be either synchronous or asynchronous. If the external
abort is synchronous then the result is:
a synchronous Prefetch Abort exception if the translation table walk is for an instruction fetch
a synchronous Data Abort exception if the translation table walk is for a data access.
An implementation can report the error in the translation table walk asynchronously from executing the
instruction whose instruction fetch or memory access caused the translation table walk. In such an
implementation these aborts behave essentially as interrupts. They are masked by the CPSR.A bit when it
is set to 1, otherwise they are reported using the Data Abort exception.
Behavior of external aborts on a translation table walk caused by a VA to PA
translation
The VA to PA translation operations described in CP15 c7, Virtual Address to Physical Address translation
operations on page B3-130 require translation table walks. An external abort can occur in the translation
table walk, as described in External abort on a translation table walk. The abort generates a Data Abort
exception, and can be synchronous or asynchronous.
Parity error reporting
The ARM architecture supports the reporting of both synchronous and asynchronous parity errors from the
cache systems. It is IMPLEMENTATION DEFINED what parity errors in the cache systems, if any, result in
synchronous or asynchronous parity errors.
A fault status code is defined for reporting parity errors, see Fault Status and Fault Address registers in a
VMSA implementation on page B3-48. However when parity error reporting is implemented it is
IMPLEMENTATION DEFINED whether the assigned fault status code or another appropriate encoding is used
to report parity errors.
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