ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.312 VLD2 (single 2-element structure to all lanes)
This instruction loads one 2-element structure from memory into all lanes of two registers. For details of the
addressing mode see Advanced SIMD addressing mode on page A7-30.
Encoding T1 / A1 Advanced SIMD
VLD2. , [{@}]{!}
VLD2. , [{@}],
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 0 1 1 D 1 0 Rn Vd 1 1 0 1 size T a Rm
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 1 0 0 1 D 1 0 Rn Vd 1 1 0 1 size T a Rm
if size == ‘11’ then UNDEFINED;
ebytes = 1 31 then UNPREDICTABLE;
Assembler syntax
VLD2. , [{@}] Rm = ’1111’
VLD2. , [{@}]! Rm = ’1101’
VLD2. , [{@}], Rm = other values
where:
See Standard assembler syntax fields on page A8-7. An ARM VLD2 instruction must be
unconditional.
The data size. It must be one of:
8 encoded as size = 0b00
16 encoded as size = 0b01
32 encoded as size = 0b10.
The registers containing the structure. It must be one of:
{, } single-spaced register transfer, encoded as D:Vd = , T = 0
{, } double-spaced register transfer, encoded as D:Vd = , T = 1.
Contains the base address for the access.
The alignment. It can be one of:
16 2-byte alignment, available only if is 8, encoded as a = 1
32 4-byte alignment, available only if is 16, encoded as a = 1
A8-612 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B