ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

C10.8.2 Integration Mode Control Register (DBGITCTRL)
Debug Registers Reference
The Integration Mode Control Register, DBGITCTRL, enables the device to switch from its default
functional mode into integration mode, where the inputs and outputs of the device can be directly controlled
for integration testing or topology detection. When the processor is in integration mode, the
IMPLEMENTATION DEFINED integration registers can be used to drive output values and to read inputs.
The DBGITCTRL Register is:
debug register 960, at offset 0xF00
a read/write register
when the Security Extensions are implemented, a Common register.
The format of the DBGITCTRL Register is:
31
Bits [31:1] Reserved, UNK/SBZP.
Integration mode enable, bit [0]
Reserved, UNK/SBZP
The possible values of this bit are:
0 Normal operation
1 Integration mode enabled.
Integration mode enable
When this bit is set to 1, the device reverts to an integration mode to enable integration
testing or topology detection. The integration mode behavior is IMPLEMENTATION DEFINED.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C10-91
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