ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Note
Table C5-2 on page C5-10 does not:
Debug State
Include instructions that only update the CPSR bits that are available in the APSR, that is the N, Z,
C, V, Q, and GE[3:0] bits. These instructions have their normal behavior when executed in Debug
state.
Include instructions that cause exceptions, such as SVC, SMC, and memory access instructions that
cause aborts. The behavior of these instructions is described in Exceptions in Debug state on
page C5-20.
Show what values can be written to the CPSR. For more information, see Altering CPSR privileged
bits in Debug state on page C5-14.
MRS and MSR instructions in Debug state, in v6.1 Debug and v7 Debug
In v6.1 Debug and v7 Debug, if the debugger has to update bits in the CPSR that are not available in the
APSR then it must use the MSR instruction to do so, writing to CPSR_fsxc. The behavior of the CPSR forms
of the MSR and MRS instructions in Debug state differs from their behavior in Non-debug state. In the CPSR:
in Non-debug state:
— the execution state bits, other than the E bit, are RAZ when read by an MRS instruction
— writes to the execution state bits, other than the E bit, by an MSR instruction are ignored
in Debug state:
— the execution state bits return their correct values when read by an MRS instruction
— writes to the execution state bits by an MSR instruction update the execution state bits.
MRS and MSR instructions that read and write an SPSR behave as they do in Non-debug state.
In addition, in Debug state in v6.1 Debug and v7 Debug:
if you use an MSR instruction to directly modify the execution state bits of the CPSR, you must then
perform an Instruction Synchronization Barrier (ISB) operation
an MSR instruction that does not write to all fields of the CPSR is UNPREDICTABLE
if an MRS instruction reads the CPSR after an MSR writes the execution state bits, and before an ISB,
the value returned is UNKNOWN
if the processor leaves Debug state after an MSR writes the execution state bits, and before an ISB, the
behavior of the processor is UNPREDICTABLE.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C5-11