05.02.2013 Views

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

SHOW MORE
SHOW LESS

You also want an ePaper? Increase the reach of your titles

YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.

Debug Events<br />

When Monitor debug-mode is configured, debuggers must avoid these cases by restricting the programming<br />

of the debug event control registers:<br />

DBGVCR[28,27,12,11,4,3] must be programmed as zero, see Vector Catch Register (DBGVCR) on<br />

page C10-67.<br />

The permitted values of the Privileged Mode control bits, DBGBCR[2:1], must be restricted in the<br />

following cases:<br />

— if DBGBCR[22:20] is set to 0b010, selecting an Unlinked Context ID breakpoint<br />

— If DBGBCR[22:20] is set to 0b100 or 0b101, selecting an IVA mismatch breakpoint.<br />

For these cases, DBGBCR[2:1] must be programmed to one of:<br />

— 0b00, selecting match only in User, Supervisor or System mode<br />

— 0b10, selecting match only in User mode.<br />

See Debug exceptions in abort h<strong>and</strong>lers for additional points that must be considered before using<br />

the 0b00 setting.<br />

For details of programming the DBGBCR see Breakpoint Control Registers (DBGBCR) on<br />

page C10-49.<br />

If these restrictions are not followed, processor behavior on a resulting debug event is UNPREDICTABLE.<br />

When the Security Extensions are implemented Vector Catch debug events on the Secure Monitor Call<br />

vector are not ignored <strong>and</strong> are not UNPREDICTABLE. However, normally DBGVCR[10] is also programmed<br />

as zero, see Monitor debug-mode vector catch on Secure Monitor Call on page C3-26.<br />

Debug exceptions in abort h<strong>and</strong>lers<br />

The previous section indicated that, in <strong>ARM</strong>v7, a debugger might set DBGBCR[2:1] to 0b00, match in User,<br />

Supervisor <strong>and</strong> System modes, to avoid the possibility of reaching an unrecoverable state in the Unlinked<br />

Context ID <strong>and</strong> IVA mismatch breakpoint cases when Monitor debug-mode is selected. However,<br />

DBGBCR[2:1] must only be programmed to 0b00 if you are confident that the abort h<strong>and</strong>ler will not switch<br />

to one of these modes before saving context that might be corrupted by an additional debug event. The<br />

context that might be corrupted by such an event includes LR_abt, SPSR_abt, IFAR, DFAR, <strong>and</strong> DFSR.<br />

It is unlikely that an abort h<strong>and</strong>ler would switch to User mode to process an abort before saving these<br />

registers, so setting DBGBCR[2:1] to 0b10, match only in User mode, is safer.<br />

Also, take care when setting a Breakpoint or BKPT Instruction debug event inside a Prefetch Abort or Data<br />

Abort h<strong>and</strong>ler, or when setting a Watchpoint debug event on a data address that might be accessed by any<br />

of these h<strong>and</strong>lers.<br />

In general, a user must only set Breakpoint or BKPT Instruction debug events inside an abort h<strong>and</strong>ler at a<br />

point after the context that would be corrupted by a debug event has been saved. Breakpoint debug events<br />

in code that might be run by an abort h<strong>and</strong>ler can be avoided by setting DBGBCR[2:1] to 0b00 or 0b01, as<br />

appropriate.<br />

Watchpoint debug events in abort h<strong>and</strong>lers can be avoided by setting DBGWCR[2:1] for the watchpoint to<br />

0b10, match only unprivileged accesses, if the code being debugged is not running in a privileged mode.<br />

<strong>ARM</strong> DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. C3-25

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!