ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The System Level Programmers’ Model
Note
You can return to the SMC instruction itself by returning using a subtraction of 4, without any adjustment to
the SPSR.IT[7:0] bits. The result is that the return occurs, then interrupts or external aborts might occur and
be handled, then the SMC instruction is re-executed and another SMC exception occurs.
This relies on:
the SMC instruction being used correctly, either outside an IT block or as the last instruction in an IT
block, so that the SPSR.IT[7:0] bits indicate unconditional execution
the SMC handler not changing the result of the original conditional execution test for the SMC
instruction.
B1.6.14 Prefetch Abort exception
A Prefetch Abort exception can be generated by:
A synchronous memory abort on an instruction fetch.
Note
Asynchronous aborts on instruction fetches are reported using the Data Abort exception, see Data
Abort exception on page B1-55.
Prefetch Abort exception entry is synchronous to the instruction whose instruction fetch aborted. If
an implementation prefetches instructions, it must handle a synchronous abort on an instruction
prefetch by:
— generating a Prefetch Abort exception if and when the instruction is about to execute
— ignoring the abort if the instruction does not reach the point of being about to execute, for
example, if a branch misprediction or exception entry occurs before the instruction is reached.
For more information about memory aborts see:
— VMSA memory aborts on page B3-40
— PMSA memory aborts on page B4-13.
A Breakpoint, Vector Catch or BKPT Instruction debug event, see Debug exception on Breakpoint,
BKPT Instruction or Vector Catch debug events on page C4-2.
The following pseudocode describes how this exception is taken:
// TakePrefetchAbortException()
// ============================
TakePrefetchAbortException()
// Determine return information. SPSR is to be the current CPSR, and LR is to be the
// current PC minus 0 for Thumb or 4 for ARM, to change the PC offsets of 4 or 8
// respectively from the address of the current instruction into the required address
// of the current instruction plus 4.
new_lr_value = if CPSR.T == ‘1’ then PC else PC-4;
B1-54 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B