ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
BL{X}
where:
Instruction Details
See Standard assembler syntax fields on page A8-7. An ARM BLX (immediate) instruction
must be unconditional.
X If present, specifies a change of instruction set (from ARM to Thumb or from Thumb to
ARM). If X is omitted, the processor remains in the same state. For ThumbEE code,
specifying X is not permitted.
The label of the instruction that is to be branched to.
For BL (encodings T1, A1), the assembler calculates the required value of the offset from the
PC value of the BL instruction to this label, then selects an encoding that sets imm32 to that
offset. Permitted offsets are even numbers in the range –16777216 to 16777214 (Thumb) or
multiples of 4 in the range −33554432 to 33554428 (ARM).
For BLX (encodings T2, A2), the assembler calculates the required value of the offset from
the Align(PC,4) value of the BLX instruction to this label, then selects an encoding that sets
imm32 to that offset. Permitted offsets are multiples of 4 in the range –16777216 to 16777212
(Thumb) or even numbers in the range −33554432 to 33554430 (ARM).
Operation
if ConditionPassed() then
EncodingSpecificOperations();
if CurrentInstrSet == InstrSet_ARM then
next_instr_addr = PC - 4;
LR = next_instr_addr;
else
next_instr_addr = PC;
LR = next_instr_addr : ‘1’;
if toARM then
SelectInstrSet(InstrSet_ARM);
BranchWritePC(Align(PC,4) + imm32);
else
SelectInstrSet(InstrSet_Thumb);
BranchWritePC(PC + imm32);
Exceptions
None.
Branch range before ARMv6T2
Before ARMv6T2, J1 and J2 in encodings T1 and T2 were both 1, resulting in a smaller branch range. The
instructions could be executed as two separate 16-bit instructions, as described in BL and BLX (immediate)
instructions, before ARMv6T2 on page AppxG-4.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-59