ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Chapter C1 Introduction to the ARM Debug Architecture This chapter introduces part C of this manual, and the ARM Debug architecture. It contains the following sections: Scope of part C of this manual on page C1-2 About the ARM Debug architecture on page C1-3 Security Extensions and debug on page C1-8 Register interfaces on page C1-9. ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C1-1
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® ARM Architecture Reference Manua
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This ARM Architecture Reference Man
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Contents ARM Architecture Reference
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Contents Chapter A6 Thumb Instructi
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Contents C1.3 Security Extensions a
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Contents Appendix D Deprecated and
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Preface This preface summarizes the
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Using this manual The information i
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Part D, Appendices This manual cont
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Assembler syntax descriptions This
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Feedback ARM welcomes feedback on i
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Part A Application Level Architectu
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Introduction to the ARM Architectur
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Application Level Programmers’ Mo
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Application Level Memory Model A3.1
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Application Level Memory Model The
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Application Level Memory Model Reve
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Application Level Memory Model When
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Application Level Memory Model Open
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Application Level Memory Model Excl
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Application Level Memory Model If t
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Application Level Memory Model Memo
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Application Level Memory Model If a
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Application Level Memory Model Non-
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Application Level Memory Model Writ
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Application Level Memory Model All
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Application Level Memory Model To e
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Application Level Memory Model a re
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Application Level Memory Model A1 I
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Application Level Memory Model The
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Application Level Memory Model In a
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The Instruction Sets A4.1 About the
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The Instruction Sets A4.2 Unified A
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The Instruction Sets This alternati
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The Instruction Sets A4.4 Data-proc
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The Instruction Sets Instruction Mn
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The Instruction Sets Signed Most Si
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The Instruction Sets A4.4.5 Packing
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The Instruction Sets A4.4.7 Paralle
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The Instruction Sets A4.5 Status re
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The Instruction Sets A4.6.3 Unprivi
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The Instruction Sets A4.7 Load/stor
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The Instruction Sets A4.9 Exception
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The Instruction Sets A4.11 Advanced
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The Instruction Sets Table A4-14 El
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The Instruction Sets A4.13 Advanced
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The Instruction Sets Table A4-16 Ad
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The Instruction Sets A4.13.4 Advanc
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The Instruction Sets A4.13.6 Miscel
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The Instruction Sets A4.14 VFP data
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ARM Instruction Set Encoding A5.1 A
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ARM Instruction Set Encoding A5.2 D
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ARM Instruction Set Encoding Table
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ARM Instruction Set Encoding A5.2.3
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ARM Instruction Set Encoding Carry
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ARM Instruction Set Encoding 1 xx1x
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ARM Instruction Set Encoding A5.6 S
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ARM Instruction Set Encoding A5.7 U
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ARM Instruction Set Encoding 110x00
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Thumb Instruction Set Encoding A6.1
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Thumb Instruction Set Encoding If t
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Thumb Instruction Set Encoding If-T
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Thumb Instruction Set Encoding Tabl
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Thumb Instruction Set Encoding Carr
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Thumb Instruction Set Encoding 0100
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Thumb Instruction Set Encoding Tabl
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Thumb Instruction Set Encoding op1
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Thumb Instruction Set Encoding A6-4
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Advanced SIMD and VFP Instruction E
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Instruction Details A8.1 Format of
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Instruction Details A8.1.4 Assemble
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Instruction Details A8.1.6 Exceptio
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Instruction Details A8.3 Conditiona
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Instruction Details A8.4 Shifts app
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Instruction Details if imm5 == ‘0
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Instruction Details A8.6 Alphabetic
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Instruction Details A8.6.2 ADC (reg
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Instruction Details A8.6.3 ADC (reg
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Instruction Details A8.6.4 ADD (imm
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Instruction Details A8.6.5 ADD (imm
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Instruction Details A8.6.6 ADD (reg
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Instruction Details A8.6.7 ADD (reg
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Instruction Details A8.6.8 ADD (SP
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Instruction Details A8.6.9 ADD (SP
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Instruction Details A8.6.10 ADR Thi
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Instruction Details A8.6.11 AND (im
Page 348 and 349:
Instruction Details A8.6.12 AND (re
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Instruction Details A8.6.13 AND (re
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Instruction Details A8.6.14 ASR (im
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Instruction Details A8.6.15 ASR (re
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Instruction Details A8.6.16 B Branc
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Instruction Details A8.6.17 BFC Bit
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Instruction Details A8.6.18 BFI Bit
Page 362 and 363:
Instruction Details A8.6.19 BIC (im
Page 364 and 365:
Instruction Details A8.6.20 BIC (re
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Instruction Details A8.6.21 BIC (re
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Instruction Details A8.6.22 BKPT Br
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Instruction Details A8.6.23 BL, BLX
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Instruction Details A8.6.24 BLX (re
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Instruction Details A8.6.25 BX Bran
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Instruction Details A8.6.26 BXJ Bra
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Instruction Details A8.6.27 CBNZ, C
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Instruction Details A8.6.28 CDP, CD
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Instruction Details A8.6.29 CHKA A8
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Instruction Details A8.6.31 CLZ Cou
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Instruction Details A8.6.32 CMN (im
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Instruction Details A8.6.33 CMN (re
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Instruction Details A8.6.34 CMN (re
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Instruction Details A8.6.35 CMP (im
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Instruction Details A8.6.36 CMP (re
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Instruction Details A8.6.37 CMP (re
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Instruction Details A8.6.38 CPS A8.
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Instruction Details A8.6.40 DBG Deb
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Instruction Details A8.6.41 DMB Dat
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Instruction Details A8.6.42 DSB Dat
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Instruction Details A8.6.43 ENTERX
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Instruction Details A8.6.45 EOR (re
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Instruction Details A8.6.46 EOR (re
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Instruction Details A8.6.47 F* (for
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Instruction Details A8.6.48 HB, HBL
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Instruction Details A8.6.50 IT If T
Page 418 and 419:
Instruction Details A8.6.51 LDC, LD
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Instruction Details A8.6.52 LDC, LD
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Instruction Details A8.6.53 LDM / L
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Instruction Details A8.6.54 LDMDA /
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Instruction Details A8.6.55 LDMDB /
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Instruction Details A8.6.56 LDMIB /
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Instruction Details A8.6.57 LDR (im
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Instruction Details A8.6.58 LDR (im
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Instruction Details A8.6.59 LDR (li
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Instruction Details A8.6.60 LDR (re
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Instruction Details A8.6.61 LDRB (i
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Instruction Details A8.6.62 LDRB (i
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Instruction Details A8.6.63 LDRB (l
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Instruction Details A8.6.64 LDRB (r
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Instruction Details A8.6.65 LDRBT L
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Instruction Details A8.6.66 LDRD (i
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Instruction Details A8.6.67 LDRD (l
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Instruction Details A8.6.68 LDRD (r
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Instruction Details A8.6.69 LDREX L
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Instruction Details A8.6.70 LDREXB
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Instruction Details A8.6.71 LDREXD
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Instruction Details A8.6.72 LDREXH
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Instruction Details A8.6.73 LDRH (i
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Instruction Details A8.6.74 LDRH (i
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Instruction Details A8.6.75 LDRH (l
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Instruction Details A8.6.76 LDRH (r
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Instruction Details A8.6.77 LDRHT L
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Instruction Details A8.6.78 LDRSB (
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Instruction Details A8.6.81 LDRSBT
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Instruction Details A8.6.82 LDRSH (
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Instruction Details A8.6.85 LDRSHT
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Instruction Details A8.6.86 LDRT Lo
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Instruction Details A8.6.87 LEAVEX
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Instruction Details A8.6.89 LSL (re
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Instruction Details A8.6.90 LSR (im
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Instruction Details A8.6.91 LSR (re
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Instruction Details A8.6.92 MCR, MC
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Instruction Details A8.6.93 MCRR, M
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Instruction Details A8.6.94 MLA Mul
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Instruction Details A8.6.95 MLS Mul
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Instruction Details A8.6.96 MOV (im
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Instruction Details A8.6.97 MOV (re
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Instruction Details A8.6.98 MOV (sh
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Instruction Details A8.6.99 MOVT Mo
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Instruction Details A8.6.100 MRC, M
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Instruction Details A8.6.101 MRRC,
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Instruction Details A8.6.102 MRS Mo
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Instruction Details A8.6.103 MSR (i
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Instruction Details A8.6.104 MSR (r
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Instruction Details A8.6.105 MUL Mu
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Instruction Details A8.6.106 MVN (i
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Instruction Details A8.6.107 MVN (r
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Instruction Details A8.6.108 MVN (r
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Instruction Details A8.6.109 NEG Ne
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Instruction Details A8.6.110 NOP No
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Instruction Details A8.6.111 ORN (i
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Instruction Details A8.6.112 ORN (r
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Instruction Details A8.6.113 ORR (i
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Instruction Details A8.6.114 ORR (r
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Instruction Details A8.6.115 ORR (r
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Instruction Details A8.6.116 PKH Pa
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Instruction Details A8.6.117 PLD, P
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Instruction Details A8.6.118 PLD (l
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Instruction Details A8.6.119 PLD, P
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Instruction Details A8.6.120 PLI (i
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Instruction Details A8.6.121 PLI (r
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Instruction Details A8.6.122 POP Po
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Instruction Details A8.6.123 PUSH P
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Instruction Details A8.6.124 QADD S
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Instruction Details A8.6.125 QADD16
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Instruction Details A8.6.126 QADD8
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Instruction Details A8.6.127 QASX S
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Instruction Details A8.6.128 QDADD
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Instruction Details A8.6.129 QDSUB
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Instruction Details A8.6.130 QSAX S
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Instruction Details A8.6.131 QSUB S
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Instruction Details A8.6.132 QSUB16
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Instruction Details A8.6.133 QSUB8
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Instruction Details A8.6.134 RBIT R
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Instruction Details A8.6.135 REV By
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Instruction Details A8.6.136 REV16
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Instruction Details A8.6.137 REVSH
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Instruction Details A8.6.138 RFE Re
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Instruction Details A8.6.140 ROR (r
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Instruction Details A8.6.141 RRX Ro
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Instruction Details A8.6.142 RSB (i
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Instruction Details A8.6.143 RSB (r
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Instruction Details A8.6.144 RSB (r
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Instruction Details A8.6.145 RSC (i
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Instruction Details A8.6.146 RSC (r
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Instruction Details A8.6.147 RSC (r
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Instruction Details A8.6.148 SADD16
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Instruction Details A8.6.149 SADD8
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Instruction Details A8.6.150 SASX S
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Instruction Details A8.6.151 SBC (i
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Instruction Details A8.6.152 SBC (r
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Instruction Details A8.6.153 SBC (r
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Instruction Details A8.6.154 SBFX S
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Instruction Details A8.6.155 SDIV S
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Instruction Details A8.6.156 SEL Se
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Instruction Details A8.6.157 SETEND
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Instruction Details A8.6.158 SEV Se
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Instruction Details A8.6.159 SHADD1
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Instruction Details A8.6.160 SHADD8
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Instruction Details A8.6.161 SHASX
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Instruction Details A8.6.162 SHSAX
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Instruction Details A8.6.163 SHSUB1
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Instruction Details A8.6.164 SHSUB8
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Instruction Details A8.6.165 SMC (p
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Instruction Details A8.6.167 SMLAD
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Instruction Details A8.6.168 SMLAL
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Instruction Details A8.6.169 SMLALB
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Instruction Details A8.6.170 SMLALD
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Instruction Details A8.6.171 SMLAWB
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Instruction Details A8.6.172 SMLSD
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Instruction Details A8.6.173 SMLSLD
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Instruction Details A8.6.174 SMMLA
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Instruction Details A8.6.175 SMMLS
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Instruction Details A8.6.176 SMMUL
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Instruction Details A8.6.177 SMUAD
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Instruction Details A8.6.178 SMULBB
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Instruction Details A8.6.179 SMULL
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Instruction Details A8.6.180 SMULWB
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Instruction Details A8.6.181 SMUSD
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Instruction Details A8.6.182 SRS A8
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Instruction Details A8.6.184 SSAT16
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Instruction Details A8.6.185 SSAX S
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Instruction Details A8.6.186 SSUB16
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Instruction Details A8.6.187 SSUB8
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Instruction Details A8.6.188 STC, S
Page 686 and 687:
Instruction Details A8.6.189 STM /
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Instruction Details A8.6.190 STMDA
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Instruction Details A8.6.191 STMDB
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Instruction Details A8.6.192 STMIB
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Instruction Details A8.6.193 STR (i
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Instruction Details A8.6.194 STR (i
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Instruction Details A8.6.195 STR (r
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Instruction Details A8.6.196 STRB (
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Instruction Details A8.6.199 STRBT
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Instruction Details A8.6.200 STRD (
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Instruction Details A8.6.201 STRD (
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Instruction Details A8.6.202 STREX
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Instruction Details A8.6.203 STREXB
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Instruction Details A8.6.204 STREXD
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Instruction Details A8.6.205 STREXH
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Instruction Details A8.6.206 STRH (
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Instruction Details A8.6.209 STRHT
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Instruction Details A8.6.210 STRT S
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Instruction Details A8.6.211 SUB (i
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Instruction Details A8.6.212 SUB (i
Page 734 and 735:
Instruction Details A8.6.213 SUB (r
Page 736 and 737:
Instruction Details A8.6.214 SUB (r
Page 738 and 739:
Instruction Details A8.6.215 SUB (S
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Instruction Details A8.6.216 SUB (S
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Instruction Details A8.6.217 SUBS P
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Instruction Details A8.6.219 SWP, S
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Instruction Details A8.6.220 SXTAB
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Instruction Details A8.6.221 SXTAB1
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Instruction Details A8.6.222 SXTAH
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Instruction Details A8.6.223 SXTB S
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Instruction Details A8.6.224 SXTB16
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Instruction Details A8.6.225 SXTH S
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Instruction Details A8.6.226 TBB, T
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Instruction Details A8.6.227 TEQ (i
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Instruction Details A8.6.228 TEQ (r
Page 764 and 765:
Instruction Details A8.6.229 TEQ (r
Page 766 and 767:
Instruction Details A8.6.230 TST (i
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Instruction Details A8.6.231 TST (r
Page 770 and 771:
Instruction Details A8.6.232 TST (r
Page 772 and 773:
Instruction Details A8.6.233 UADD16
Page 774 and 775:
Instruction Details A8.6.234 UADD8
Page 776 and 777:
Instruction Details A8.6.235 UASX U
Page 778 and 779:
Instruction Details A8.6.236 UBFX U
Page 780 and 781:
Instruction Details A8.6.237 UDIV U
Page 782 and 783:
Instruction Details A8.6.238 UHADD1
Page 784 and 785:
Instruction Details A8.6.239 UHADD8
Page 786 and 787:
Instruction Details A8.6.240 UHASX
Page 788 and 789:
Instruction Details A8.6.241 UHSAX
Page 790 and 791:
Instruction Details A8.6.242 UHSUB1
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Instruction Details A8.6.243 UHSUB8
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Instruction Details A8.6.244 UMAAL
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Instruction Details A8.6.245 UMLAL
Page 798 and 799:
Instruction Details A8.6.246 UMULL
Page 800 and 801:
Instruction Details A8.6.247 UQADD1
Page 802 and 803:
Instruction Details A8.6.248 UQADD8
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Instruction Details A8.6.249 UQASX
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Instruction Details A8.6.250 UQSAX
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Instruction Details A8.6.251 UQSUB1
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Instruction Details A8.6.252 UQSUB8
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Instruction Details A8.6.253 USAD8
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Instruction Details A8.6.254 USADA8
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Instruction Details A8.6.255 USAT U
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Instruction Details A8.6.256 USAT16
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Instruction Details A8.6.257 USAX U
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Instruction Details A8.6.258 USUB16
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Instruction Details A8.6.259 USUB8
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Instruction Details A8.6.260 UXTAB
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Instruction Details A8.6.261 UXTAB1
Page 830 and 831:
Instruction Details A8.6.262 UXTAH
Page 832 and 833:
Instruction Details A8.6.263 UXTB U
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Instruction Details A8.6.264 UXTB16
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Instruction Details A8.6.265 UXTH U
Page 838 and 839:
Instruction Details A8.6.266 VABA,
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Instruction Details A8.6.267 VABD,
Page 842 and 843:
Instruction Details A8.6.268 VABD (
Page 844 and 845:
Instruction Details A8.6.269 VABS V
Page 846 and 847:
Instruction Details A8.6.270 VACGE,
Page 848 and 849:
Instruction Details A8.6.271 VADD (
Page 850 and 851:
Instruction Details A8.6.272 VADD (
Page 852 and 853:
Instruction Details A8.6.273 VADDHN
Page 854 and 855:
Instruction Details A8.6.274 VADDL,
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Instruction Details A8.6.275 VAND (
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Instruction Details A8.6.277 VBIC (
Page 860 and 861:
Instruction Details A8.6.278 VBIC (
Page 862 and 863:
Instruction Details A8.6.279 VBIF,
Page 864 and 865:
Instruction Details A8.6.280 VCEQ (
Page 866 and 867:
Instruction Details A8.6.281 VCEQ (
Page 868 and 869:
Instruction Details A8.6.282 VCGE (
Page 870 and 871:
Instruction Details A8.6.283 VCGE (
Page 872 and 873:
Instruction Details A8.6.284 VCGT (
Page 874 and 875:
Instruction Details A8.6.285 VCGT (
Page 876 and 877:
Instruction Details A8.6.286 VCLE (
Page 878 and 879:
Instruction Details A8.6.288 VCLS V
Page 880 and 881:
Instruction Details A8.6.289 VCLT (
Page 882 and 883:
Instruction Details A8.6.291 VCLZ V
Page 884 and 885:
Instruction Details A8.6.292 VCMP,
Page 886 and 887:
Instruction Details A8.6.293 VCNT T
Page 888 and 889:
Instruction Details A8.6.294 VCVT (
Page 890 and 891:
Instruction Details A8.6.295 VCVT,
Page 892 and 893:
Page 894 and 895:
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Page 898 and 899:
Page 900 and 901:
Instruction Details A8.6.300 VCVTB,
Page 902 and 903:
Instruction Details A8.6.301 VDIV T
Page 904 and 905:
Instruction Details A8.6.302 VDUP (
Page 906 and 907:
Instruction Details A8.6.303 VDUP (
Page 908 and 909:
Instruction Details A8.6.304 VEOR V
Page 910 and 911:
Instruction Details A8.6.305 VEXT V
Page 912 and 913:
Instruction Details A8.6.306 VHADD,
Page 914 and 915:
Instruction Details A8.6.307 VLD1 (
Page 916 and 917:
Page 918 and 919:
Page 920 and 921:
Page 922 and 923:
Page 924 and 925:
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Page 928 and 929:
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Instruction Details A8.6.319 VLDM V
Page 940 and 941:
Instruction Details A8.6.320 VLDR T
Page 942 and 943:
Instruction Details A8.6.321 VMAX,
Page 944 and 945:
Instruction Details A8.6.322 VMAX,
Page 946 and 947:
Instruction Details A8.6.323 VMLA,
Page 948 and 949:
Page 950 and 951:
Page 952 and 953:
Instruction Details A8.6.326 VMOV (
Page 954 and 955:
Page 956 and 957:
Page 958 and 959:
Page 960 and 961:
Page 962 and 963:
Page 964 and 965:
Page 966 and 967:
Instruction Details A8.6.333 VMOVL
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Instruction Details A8.6.334 VMOVN
Page 970 and 971:
Instruction Details A8.6.335 VMRS M
Page 972 and 973:
Instruction Details A8.6.336 VMSR M
Page 974 and 975:
Instruction Details A8.6.337 VMUL,
Page 976 and 977:
Instruction Details A8.6.338 VMUL (
Page 978 and 979:
Instruction Details A8.6.339 VMUL,
Page 980 and 981:
Instruction Details A8.6.340 VMVN (
Page 982 and 983:
Instruction Details A8.6.341 VMVN (
Page 984 and 985:
Instruction Details A8.6.342 VNEG V
Page 986 and 987:
Instruction Details A8.6.343 VNMLA,
Page 988 and 989:
Instruction Details A8.6.344 VORN (
Page 990 and 991:
Instruction Details A8.6.346 VORR (
Page 992 and 993:
Instruction Details A8.6.347 VORR (
Page 994 and 995:
Instruction Details A8.6.348 VPADAL
Page 996 and 997:
Instruction Details A8.6.349 VPADD
Page 998 and 999:
Instruction Details A8.6.350 VPADD
Page 1000 and 1001:
Instruction Details A8.6.351 VPADDL
Page 1002 and 1003:
Instruction Details A8.6.352 VPMAX,
Page 1004 and 1005:
Instruction Details A8.6.353 VPMAX,
Page 1006 and 1007:
Instruction Details A8.6.354 VPOP V
Page 1008 and 1009:
Instruction Details A8.6.355 VPUSH
Page 1010 and 1011:
Instruction Details A8.6.356 VQABS
Page 1012 and 1013:
Instruction Details A8.6.357 VQADD
Page 1014 and 1015:
Instruction Details A8.6.358 VQDMLA
Page 1016 and 1017:
Instruction Details A8.6.359 VQDMUL
Page 1018 and 1019:
Instruction Details A8.6.360 VQDMUL
Page 1020 and 1021:
Instruction Details A8.6.361 VQMOVN
Page 1022 and 1023:
Instruction Details A8.6.362 VQNEG
Page 1024 and 1025:
Instruction Details A8.6.363 VQRDMU
Page 1026 and 1027:
Instruction Details A8.6.364 VQRSHL
Page 1028 and 1029:
Instruction Details A8.6.365 VQRSHR
Page 1030 and 1031:
Instruction Details A8.6.366 VQSHL
Page 1032 and 1033:
Instruction Details A8.6.367 VQSHL,
Page 1034 and 1035:
Instruction Details A8.6.368 VQSHRN
Page 1036 and 1037:
Instruction Details A8.6.369 VQSUB
Page 1038 and 1039:
Instruction Details A8.6.370 VRADDH
Page 1040 and 1041:
Instruction Details A8.6.371 VRECPE
Page 1042 and 1043:
Instruction Details A8.6.372 VRECPS
Page 1044 and 1045:
Instruction Details A8.6.373 VREV16
Page 1046 and 1047:
Instruction Details A8.6.374 VRHADD
Page 1048 and 1049:
Instruction Details A8.6.375 VRSHL
Page 1050 and 1051:
Instruction Details A8.6.376 VRSHR
Page 1052 and 1053:
Instruction Details A8.6.377 VRSHRN
Page 1054 and 1055:
Instruction Details A8.6.378 VRSQRT
Page 1056 and 1057:
Instruction Details A8.6.379 VRSQRT
Page 1058 and 1059:
Instruction Details A8.6.380 VRSRA
Page 1060 and 1061:
Instruction Details A8.6.381 VRSUBH
Page 1062 and 1063:
Instruction Details A8.6.382 VSHL (
Page 1064 and 1065:
Instruction Details A8.6.383 VSHL (
Page 1066 and 1067:
Instruction Details A8.6.384 VSHLL
Page 1068 and 1069:
Instruction Details A8.6.385 VSHR V
Page 1070 and 1071:
Instruction Details A8.6.386 VSHRN
Page 1072 and 1073:
Instruction Details A8.6.387 VSLI V
Page 1074 and 1075:
Instruction Details A8.6.388 VSQRT
Page 1076 and 1077:
Instruction Details A8.6.389 VSRA V
Page 1078 and 1079:
Instruction Details A8.6.390 VSRI V
Page 1080 and 1081:
Instruction Details A8.6.391 VST1 (
Page 1082 and 1083:
Page 1084 and 1085:
Page 1086 and 1087:
Page 1088 and 1089:
Page 1090 and 1091:
Page 1092 and 1093:
Page 1094 and 1095:
Page 1096 and 1097:
Instruction Details A8.6.399 VSTM V
Page 1098 and 1099:
Instruction Details A8.6.400 VSTR T
Page 1100 and 1101:
Instruction Details A8.6.401 VSUB (
Page 1102 and 1103:
Instruction Details A8.6.402 VSUB (
Page 1104 and 1105:
Instruction Details A8.6.403 VSUBHN
Page 1106 and 1107:
Instruction Details A8.6.404 VSUBL,
Page 1108 and 1109:
Instruction Details A8.6.405 VSWP V
Page 1110 and 1111:
Instruction Details A8.6.406 VTBL,
Page 1112 and 1113:
Instruction Details A8.6.407 VTRN D
Page 1114 and 1115:
Instruction Details A8.6.408 VTST V
Page 1116 and 1117:
Instruction Details A8.6.409 VUZP V
Page 1118 and 1119:
Instruction Details A8.6.410 VZIP V
Page 1120 and 1121:
Instruction Details A8.6.411 WFE Wa
Page 1122 and 1123:
Instruction Details A8.6.412 WFI Wa
Page 1124 and 1125:
Instruction Details A8.6.413 YIELD
Page 1126 and 1127:
Instruction Details A8-814 Copyrigh
Page 1128 and 1129:
ThumbEE A9.1 The ThumbEE instructio
Page 1130 and 1131:
ThumbEE A9.1.3 Instructions with mo
Page 1132 and 1133:
ThumbEE A9.2 ThumbEE instruction se
Page 1134 and 1135:
ThumbEE A9.4 ThumbEE instructions w
Page 1136 and 1137:
ThumbEE A9.4.2 LDRH (register) Load
Page 1138 and 1139:
ThumbEE A9.4.4 STR (register) Store
Page 1140 and 1141:
ThumbEE A9.5 Additional ThumbEE ins
Page 1142 and 1143:
ThumbEE A9.5.2 HB, HBL Handler Bran
Page 1144 and 1145:
ThumbEE A9.5.4 HBP HBP (Handler Bra
Page 1146 and 1147:
ThumbEE Assembler syntax LDR , [{,
Page 1148 and 1149:
ThumbEE A9-22 Copyright © 1996-199
Page 1151 and 1152:
Chapter B1 The System Level Program
Page 1153 and 1154:
B1.2 System level concepts and term
Page 1155 and 1156:
An exception is described as synchr
Page 1157 and 1158:
Notes on the ARM processor modes Th
Page 1159 and 1160:
B1.3.2 ARM core registers The Syste
Page 1161 and 1162:
Writing to the PC In ARMv7, instruc
Page 1163 and 1164:
LookUpRName() // ============= The
Page 1165 and 1166:
interrupt and asynchronous abort di
Page 1167 and 1168:
Mask bits, bits [8:6] The System Le
Page 1169 and 1170:
The System Level Programmers’ Mod
Page 1171 and 1172:
SPSR[] = bits(32) value if BadMode(
Page 1173 and 1174:
B1.4 Instruction set states The Sys
Page 1175 and 1176:
B1.5 The Security Extensions The Sy
Page 1177 and 1178:
Note It is important to distinguish
Page 1179 and 1180:
Page 1181 and 1182:
Exception offset Exception that is
Page 1183 and 1184:
Operation The System Level Programm
Page 1185 and 1186:
Exception Base LR value a Instructi
Page 1187 and 1188:
Exception The System Level Programm
Page 1189 and 1190:
Page 1191 and 1192:
B1.6.5 Exception-handling instructi
Page 1193 and 1194:
SCR bits FW FIQ Effect on FIQ handl
Page 1195 and 1196:
Page 1197 and 1198:
Page 1199 and 1200:
Page 1201 and 1202:
Page 1203 and 1204:
B1.6.13 Secure Monitor Call (SMC) e
Page 1205 and 1206:
new_spsr_value = CPSR; The System L
Page 1207 and 1208:
CPSR.J = ‘0’; CPSR.T = SCTLR.TE
Page 1209 and 1210:
Page 1211 and 1212:
Page 1213 and 1214:
Page 1215 and 1216:
Page 1217 and 1218:
Note The System Level Programmers
Page 1219 and 1220:
Page 1221 and 1222:
In addition: The System Level Progr
Page 1223 and 1224:
B1.9 Execution environment support
Page 1225 and 1226:
Page 1227 and 1228:
Jazelle state configuration and con
Page 1229 and 1230:
Controlling entry to Jazelle state
Page 1231 and 1232:
Trivial implementation of the Jazel
Page 1233 and 1234:
Page 1235 and 1236:
Chapter B2 Common Memory System Arc
Page 1237 and 1238:
B2.2 Caches Common Memory System Ar
Page 1239 and 1240:
B2.2.2 Cache behavior Common Memory
Page 1241 and 1242:
Common Memory System Architecture F
Page 1243 and 1244:
Note Common Memory System Architect
Page 1245 and 1246:
Page 1247 and 1248:
Page 1249 and 1250:
Page 1251 and 1252:
Page 1253 and 1254:
implement one of the other permitte
Page 1255 and 1256:
Page 1257 and 1258:
Page 1259 and 1260:
Page 1261 and 1262:
B2.3 IMPLEMENTATION DEFINED memory
Page 1263 and 1264:
Page 1265 and 1266:
when MemArch_PMSA AlignmentFaultP(a
Page 1267 and 1268:
Page 1269 and 1270:
B2.4.7 Exclusive monitors operation
Page 1271 and 1272:
B2.4.8 Access permission checking C
Page 1273 and 1274:
B2.4.10 Data Abort exception Common
Page 1275 and 1276:
Chapter B3 Virtual Memory System Ar
Page 1277 and 1278:
Virtual Memory System Architecture
Page 1279 and 1280:
B3.2.3 Enabling and disabling the M
Page 1281 and 1282:
B3.3 Translation tables Virtual Mem
Page 1283 and 1284:
The other fields in the descriptors
Page 1285 and 1286:
Additional requirements for transla
Page 1287 and 1288:
B3.3.3 Translation table walks Virt
Page 1289 and 1290:
Page 1291 and 1292:
Translation flow for a Section Virt
Page 1293 and 1294:
Translation flow for a Small page V
Page 1295 and 1296:
B3.3.4 Changing translation table a
Page 1297 and 1298:
B3.4 Address mapping restrictions V
Page 1299 and 1300:
Note Virtual Memory System Architec
Page 1301 and 1302:
B3.5.1 The effect of the Security E
Page 1303 and 1304:
AP[2] AP[1:0] Virtual Memory System
Page 1305 and 1306:
B3.6.3 Domains Virtual Memory Syste
Page 1307 and 1308:
Page 1309 and 1310:
Page 1311 and 1312:
Page 1313 and 1314:
B3.7.4 The effect of the Security E
Page 1315 and 1316:
Section domain fault Section permis
Page 1317 and 1318:
Translation fault There are two typ
Page 1319 and 1320:
B3.8.2 External aborts Virtual Memo
Page 1321 and 1322:
Page 1323 and 1324:
Page 1325 and 1326:
DFSR [10,3:0] a Virtual Memory Syst
Page 1327 and 1328:
B3.9.8 Auxiliary Fault Status Regis
Page 1329 and 1330:
B3.10.2 TLB matching Virtual Memory
Page 1331 and 1332:
In the TLB operations: Virtual Memo
Page 1333 and 1334:
Page 1335 and 1336:
Page 1337 and 1338:
Page 1339 and 1340:
Page 1341 and 1342:
Register and description c1, Secure
Page 1343 and 1344:
Page 1345 and 1346:
Page 1347 and 1348:
CP15 register Virtual Memory System
Page 1349 and 1350:
CP15 register Virtual Memory System
Page 1351 and 1352:
Page 1353 and 1354:
B3.12.6 CP15 c0, ID codes registers
Page 1355 and 1356:
B3.12.7 c0, Main ID Register (MIDR)
Page 1357 and 1358:
Accessing the MIDR Virtual Memory S
Page 1359 and 1360:
B3.12.9 c0, TCM Type Register (TCMT
Page 1361 and 1362:
B3.12.11 c0, Multiprocessor Affinit
Page 1363 and 1364:
Page 1365 and 1366:
B3.12.12 c0, Cache Size ID Register
Page 1367 and 1368:
CtypeX, bits [3(x - 1) + 2:3(x - 1)
Page 1369 and 1370:
B3.12.15 c0, Cache Size Selection R
Page 1371 and 1372:
When the Security Extensions are im
Page 1373 and 1374:
Bit [23] RAO/SBOP. Virtual Memory S
Page 1375 and 1376:
Page 1377 and 1378:
Accessing the SCTLR Virtual Memory
Page 1379 and 1380:
Page 1381 and 1382:
nET, bit [6] Not Early Termination.
Page 1383 and 1384:
The format of the SDER is: 31 Bits
Page 1385 and 1386:
NSASEDIS, bit[15] Disable Non-secur
Page 1387 and 1388:
B3.12.23 CP15 c2 and c3, Memory pro
Page 1389 and 1390:
Page 1391 and 1392:
C, bit [0], ARMv7-A base architectu
Page 1393 and 1394:
Accessing the TTBCR Virtual Memory
Page 1395 and 1396:
B3.12.28 CP15 c5, Fault status regi
Page 1397 and 1398:
Page 1399 and 1400:
Accessing the DFAR Virtual Memory S
Page 1401 and 1402:
Page 1403 and 1404:
Set/way Virtual Memory System Archi
Page 1405 and 1406:
Page 1407 and 1408:
Page 1409 and 1410:
Page 1411 and 1412:
CP15 c7, Data and Instruction Barri
Page 1413 and 1414:
The CP15 c8 TLB maintenance functio
Page 1415 and 1416:
Invalidate TLB entries by MVA all A
Page 1417 and 1418:
The IMPLEMENTATION DEFINED TLB cont
Page 1419 and 1420:
Page 1421 and 1422:
10 Region is WriteThrough, Non-Writ
Page 1423 and 1424:
Page 1425 and 1426:
Page 1427 and 1428:
Page 1429 and 1430:
Accessing the Software Thread ID re
Page 1431 and 1432:
B3.13.3 Address translation Virtual
Page 1433 and 1434:
Page 1435 and 1436:
domain = bits(4) UNKNOWN; sectionno
Page 1437 and 1438:
Chapter B4 Protected Memory System
Page 1439 and 1440:
All addresses are physical addresse
Page 1441 and 1442:
Using the default memory map as a b
Page 1443 and 1444:
Address range Behavior of an implem
Page 1445 and 1446:
B4.2 Memory access control Protecte
Page 1447 and 1448:
B4.3 Memory region attributes Prote
Page 1449 and 1450:
B4.4 PMSA memory aborts Protected M
Page 1451 and 1452:
The MPU fault checking sequence Fig
Page 1453 and 1454:
Parity error reporting Protected Me
Page 1455 and 1456:
B4.5.2 Data Abort exceptions Protec
Page 1457 and 1458:
Reserved encodings in the IFSR and
Page 1459 and 1460:
Protected Memory System Architectur
Page 1461 and 1462:
Page 1463 and 1464:
Unallocated CP15 encodings Protecte
Page 1465 and 1466:
B4.6.4 Meaning of fixed bit values
Page 1467 and 1468:
Page 1469 and 1470:
Architecture, bits [19:16] Table B4
Page 1471 and 1472:
DminLine, bits [19:16] Bit [15] RAO
Page 1473 and 1474:
Page 1475 and 1476:
Page 1477 and 1478:
LineSize, bits [2:0] (Log2(Number o
Page 1479 and 1480:
B4.6.13 c0, IMPLEMENTATION DEFINED
Page 1481 and 1482:
B4.6.16 c1, System Control Register
Page 1483 and 1484:
Bit [20] RAZ/SBZP. Protected Memory
Page 1485 and 1486:
Page 1487 and 1488:
Accessing the ACTLR Protected Memor
Page 1489 and 1490:
Page 1491 and 1492:
Page 1493 and 1494:
The formats of the ADFSR and AIFSR
Page 1495 and 1496:
B4.6.24 CP15 c6, Memory region prog
Page 1497 and 1498:
The DRBAR is: a 32-bit read/write r
Page 1499 and 1500:
RSize, bits [5:1] Protected Memory
Page 1501 and 1502:
Page 1503 and 1504:
Page 1505 and 1506:
Page 1507 and 1508:
Set/way Protected Memory System Arc
Page 1509 and 1510:
Instruction Synchronization Barrier
Page 1511 and 1512:
B4.6.31 CP15 c11, Reserved for TCM
Page 1513 and 1514:
B4.6.35 CP15 c13 Software Thread ID
Page 1515 and 1516:
Page 1517 and 1518:
B4.7.3 Default memory map attribute
Page 1519 and 1520:
Chapter B5 The CPUID Identification
Page 1521 and 1522:
B5.1.2 General features of the CPUI
Page 1523 and 1524:
State1, bits [7:4] The CPUID Identi
Page 1525 and 1526:
Memory-mapped trace model, bits [19
Page 1527 and 1528:
B5.2.4 CP15 c0, Memory Model Featur
Page 1529 and 1530:
c0, Memory Model Feature Register 1
Page 1531 and 1532:
The CPUID Identification Scheme 0b0
Page 1533 and 1534:
Unified TLB, bits [19:16] The CPUID
Page 1535 and 1536:
c0, Memory Model Feature Register 3
Page 1537 and 1538:
Accessing the Memory Model Feature
Page 1539 and 1540: Multiply instructions The CPUID Ide
Page 1541 and 1542: The CPUID Identification Scheme Tab
Page 1543 and 1544: Swap_instrs, bits [3:0] The CPUID I
Page 1545 and 1546: Endian_instrs, bits [3:0] The CPUID
Page 1547 and 1548: c0, Instruction Set Attribute Regis
Page 1549 and 1550: Note The CPUID Identification Schem
Page 1551 and 1552: Unpriv_instrs, bits [3:0] The CPUID
Page 1553 and 1554: The CPUID Identification Scheme SW,
Page 1555 and 1556: Square root, bits [23:20] Divide, b
Page 1557 and 1558: VFP HPFP, bits[27:24] The CPUID Ide
Page 1559 and 1560: Chapter B6 System Instructions This
Page 1561 and 1562: B6.1.1 CPS System Instructions Chan
Page 1563 and 1564: B6.1.2 LDM (exception return) Syste
Page 1565 and 1566: B6.1.3 LDM (user registers) System
Page 1567 and 1568: B6.1.4 LDRBT, LDRHT, LDRSBT, LDRSHT
Page 1569 and 1570: Assembler syntax MRS , where: See
Page 1571 and 1572: Operation if ConditionPassed() then
Page 1573 and 1574: Is a sequence of one or more of the
Page 1575 and 1576: Assembler syntax RFE{} {!} where:
Page 1577 and 1578: Assembler syntax SMC # where: See
Page 1579 and 1580: Assembler syntax SRS{} SP{!}, # whe
Page 1581 and 1582: Operation if ConditionPassed() then
Page 1583 and 1584: B6.1.13 SUBS PC, LR and related ins
Page 1585 and 1586: B6.1.14 VMRS System Instructions Mo
Page 1587 and 1588: B6.1.15 VMSR System Instructions Mo
Page 1589: Part C Debug Architecture
Page 1593 and 1594: C1.2 About the ARM Debug architectu
Page 1595 and 1596: C1.2.2 Non-invasive debug Introduct
Page 1597 and 1598: Introduction to the ARM Debug Archi
Page 1599 and 1600: C1.4 Register interfaces Introducti
Page 1601 and 1602: Chapter C2 Invasive Debug Authentic
Page 1603 and 1604: in Non-secure state and also in Sec
Page 1605 and 1606: Chapter C3 Debug Events This chapte
Page 1607 and 1608: BKPT Instruction Breakpoint Vector
Page 1609 and 1610: C3.2 Software debug events A Softwa
Page 1611 and 1612: Debug event generation conditions d
Page 1613 and 1614: Condition for breakpoint generation
Page 1615 and 1616: IVA mismatch with an address range
Page 1617 and 1618: Note Debug Events When programming
Page 1619 and 1620: Note Instructions that branch to th
Page 1621 and 1622: Debug Events For each of the memory
Page 1623 and 1624: Debug Events For example, if the se
Page 1625 and 1626: Debug Events One set for exceptions
Page 1627 and 1628: If the Security Extensions are impl
Page 1629 and 1630: Debug Events When Monitor debug-mod
Page 1631 and 1632: Debug Events 2. The processor takes
Page 1633 and 1634: Each unit of the instruction is che
Page 1635 and 1636: BVR_match = byte_select_match && (c
Page 1637 and 1638: eturn; VCR_Recent_IRQ_NS_Valid = TR
Page 1639 and 1640: When Monitor debug-mode is configur
Page 1641 and 1642:
when ‘10’ secure_state_match =
Page 1643 and 1644:
In v6 Debug and v6.1 Debug: Debug E
Page 1645 and 1646:
Debug Events Usually, exception ret
Page 1647 and 1648:
C3.5 Debug event prioritization Deb
Page 1649 and 1650:
Chapter C4 Debug Exceptions This ch
Page 1651 and 1652:
C4.1.2 Debug exception on Watchpoin
Page 1653 and 1654:
Debug Exceptions In Monitor debug-m
Page 1655 and 1656:
Chapter C5 Debug State This chapter
Page 1657 and 1658:
C5.2 Entering Debug state Debug Sta
Page 1659 and 1660:
C5.2.2 Asynchronous aborts and entr
Page 1661 and 1662:
C5.3 Behavior of the PC and CPSR in
Page 1663 and 1664:
C5.4 Executing instructions in Debu
Page 1665 and 1666:
Note Table C5-2 on page C5-10 does
Page 1667 and 1668:
C5.5 Privilege in Debug state Debug
Page 1669 and 1670:
Being in Debug state when invasive
Page 1671 and 1672:
Instructions for CP14 and CP15 Debu
Page 1673 and 1674:
C5.6 Behavior of non-invasive debug
Page 1675 and 1676:
Undefined Instruction Debug State U
Page 1677 and 1678:
Debug State C5.7.1 Undefined Instru
Page 1679 and 1680:
C5.8.1 Access to specific cache man
Page 1681 and 1682:
C5.8.2 Debug state Cache and MMU Co
Page 1683 and 1684:
Note Leaving Debug state is not a m
Page 1685 and 1686:
Chapter C6 Debug Register Interface
Page 1687 and 1688:
Debug Register Interfaces The Debug
Page 1689 and 1690:
Debug Register Interfaces The proto
Page 1691 and 1692:
OS Save and Restore registers, and
Page 1693 and 1694:
The OS Save and Restore mechanism i
Page 1695 and 1696:
The DCC status flags themselves:
Page 1697 and 1698:
CMP R1, #0 ; Check for zero SaveDeb
Page 1699 and 1700:
Debug Register Interfaces Example C
Page 1701 and 1702:
Table C6-1 summarizes the v7 Debug
Page 1703 and 1704:
Register number 33 0x084 Write-only
Page 1705 and 1706:
Register number C6.3.1 Internal and
Page 1707 and 1708:
C6.3.2 Effect of the Security Exten
Page 1709 and 1710:
Debug Register Interfaces Synchroni
Page 1711 and 1712:
Note Debug Register Interfaces The
Page 1713 and 1714:
Debug Register Interfaces Access to
Page 1715 and 1716:
Debug Register Interfaces When the
Page 1717 and 1718:
MRC p14,0,,c0,c5,0 STC p14,c5, MCR
Page 1719 and 1720:
Debug Register Interfaces Accesses
Page 1721 and 1722:
Note The Baseline CP14 instructions
Page 1723 and 1724:
Debug Register Interfaces v7 Debug
Page 1725 and 1726:
Debug Register Interfaces When the
Page 1727 and 1728:
Debug Register Interfaces C6.7 The
Page 1729 and 1730:
Debug Register Interfaces bits [23:
Page 1731 and 1732:
Access permissions for the external
Page 1733 and 1734:
Debug Register Interfaces Table C6-
Page 1735 and 1736:
Debug Register Interfaces C6.7.5 Re
Page 1737 and 1738:
Chapter C7 Non-invasive Debug Authe
Page 1739 and 1740:
Non-invasive Debug Authentication T
Page 1741 and 1742:
Page 1743 and 1744:
C7.3.2 Trace All instructions and d
Page 1745 and 1746:
Page 1747 and 1748:
Chapter C8 Sample-based Profiling T
Page 1749 and 1750:
Note ARM recommends that an impleme
Page 1751 and 1752:
Chapter C9 Performance Monitors Thi
Page 1753 and 1754:
The set of events that might be mon
Page 1755 and 1756:
C9.3 Accuracy of the performance mo
Page 1757 and 1758:
C9.5 Interaction with Security Exte
Page 1759 and 1760:
C9.7 Interaction with power saving
Page 1761 and 1762:
MRC p15,0,,c9,c12,4 UNPREDICTABLE.
Page 1763 and 1764:
C9.10 Event numbers The event numbe
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Performance Monitors 0x0B Instructi
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Transaction counts on external buse
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Chapter C10 Debug Registers Referen
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C10.2 Debug identification register
Page 1773 and 1774:
nSUHD_imp, bit [14] Debug Registers
Page 1775 and 1776:
Debug Registers Reference 0b0010 DB
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Debug Registers Reference One imple
Page 1779 and 1780:
In v7 Debug, the format of the DBGD
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Debug Registers Reference On a read
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Debug Registers Reference If the ex
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Debug Registers Reference If a debu
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SDABORT_l, bit [6] Debug Registers
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Debug Registers Reference Table C10
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Debug Registers Reference Debuggers
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Stalling of accesses to the DCC reg
Page 1795 and 1796:
Debug Registers Reference When debu
Page 1797 and 1798:
C10.3.3 Debug Run Control Register
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Debug state entry is the acknowledg
Page 1801 and 1802:
Note Debug Registers Reference When
Page 1803 and 1804:
Debug Registers Reference When the
Page 1805 and 1806:
Reset state Debug Registers Referen
Page 1807 and 1808:
Meaning of PC Sample Value, bits [1
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Debug Registers Reference v7 Debug
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C10.4.2 Target to Host Data Transfe
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Access mode a Debug Registers Refer
Page 1815 and 1816:
Access mode a Non- blocking Flag b
Page 1817 and 1818:
When used for IVA comparison the fo
Page 1819 and 1820:
Debug Registers Reference Bit [21],
Page 1821 and 1822:
Debug Registers Reference 0b101 Lin
Page 1823 and 1824:
Breakpoint enable, bit [0] 0b11 Mat
Page 1825 and 1826:
Page 1827 and 1828:
Linked comparisons Debug Registers
Page 1829 and 1830:
C10.5.4 Watchpoint Control Register
Page 1831 and 1832:
0b01 watchpoint generated on match
Page 1833 and 1834:
Byte address masking behavior on DV
Page 1835 and 1836:
Note Debug Registers Reference This
Page 1837 and 1838:
31 30 29 28 27 26 25 24 16 15 14 13
Page 1839 and 1840:
Vector catch operation when Securit
Page 1841 and 1842:
Page 1843 and 1844:
C10.6 OS Save and Restore registers
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Locked, bit [1] Debug Registers Ref
Page 1847 and 1848:
The format of the DBGECR is: Bits [
Page 1849 and 1850:
C10.7.1 Debug State Cache Control R
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Permitted IMPLEMENTATION DEFINED li
Page 1853 and 1854:
Debug Registers Reference It is IMP
Page 1855 and 1856:
Permitted IMPLEMENTATION DEFINED li
Page 1857 and 1858:
Register number Access a Debug Regi
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C10.8.2 Integration Mode Control Re
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C10.8.4 Claim Tag Clear Register (D
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C10.8.6 Lock Status Register (DBGLS
Page 1865 and 1866:
Non-secure invasive debug features
Page 1867 and 1868:
Note Debug Registers Reference ARMv
Page 1869 and 1870:
Revision 4 bits Revision number for
Page 1871 and 1872:
occupy the last four words of the 4
Page 1873 and 1874:
C10.9 Performance monitor registers
Page 1875 and 1876:
Debug Registers Reference X, bit [4
Page 1877 and 1878:
Table C10-25 shows the behavior of
Page 1879 and 1880:
Debug Registers Reference The forma
Page 1881 and 1882:
C10.9.6 c9, Event Counter Selection
Page 1883 and 1884:
C10.9.8 c9, Event Type Select Regis
Page 1885 and 1886:
C10.9.10 c9, User Enable Register (
Page 1887 and 1888:
Table C10-28 shows the behavior of
Page 1889:
Part D Appendices
Page 1892 and 1893:
Recommended External Debug Interfac
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Page 1896 and 1897:
Page 1898 and 1899:
Page 1900 and 1901:
Page 1902 and 1903:
Page 1904 and 1905:
Page 1906 and 1907:
Page 1908 and 1909:
Common VFP Subarchitecture Specific
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Page 1912 and 1913:
Page 1914 and 1915:
Page 1916 and 1917:
Page 1918 and 1919:
Page 1920 and 1921:
Page 1922 and 1923:
Page 1924 and 1925:
Page 1926 and 1927:
Page 1928 and 1929:
Page 1930 and 1931:
Page 1932 and 1933:
Legacy Instruction Mnemonics C.1 Th
Page 1934 and 1935:
Legacy Instruction Mnemonics AppxC-
Page 1936 and 1937:
Deprecated and Obsolete Features D.
Page 1938 and 1939:
Page 1940 and 1941:
Page 1942 and 1943:
Page 1944 and 1945:
Page 1946 and 1947:
Fast Context Switch Extension (FCSE
Page 1948 and 1949:
Page 1950 and 1951:
Page 1952 and 1953:
VFP Vector Operation Support F.1 Ab
Page 1954 and 1955:
VFP Vector Operation Support Table
Page 1956 and 1957:
VFP Vector Operation Support Scalar
Page 1958 and 1959:
VFP Vector Operation Support AppxF-
Page 1960 and 1961:
ARMv6 Differences G.1 Introduction
Page 1962 and 1963:
ARMv6 Differences ARMv6T2 supports
Page 1964 and 1965:
ARMv6 Differences G.3 Application l
Page 1966 and 1967:
ARMv6 Differences G.3.3 Semaphore s
Page 1968 and 1969:
ARMv6 Differences G.4 Instruction s
Page 1970 and 1971:
ARMv6 Differences Table G-2 ARM ins
Page 1972 and 1973:
ARMv6 Differences G.4.2 Thumb instr
Page 1974 and 1975:
ARMv6 Differences G.5 System level
Page 1976 and 1977:
ARMv6 Differences G.5.2 The excepti
Page 1978 and 1979:
ARMv6 Differences G.6 System level
Page 1980 and 1981:
ARMv6 Differences ARMv6 defines a s
Page 1982 and 1983:
ARMv6 Differences TCM CP15 configur
Page 1984 and 1985:
ARMv6 Differences VMSAv6 translatio
Page 1986 and 1987:
ARMv6 Differences TCM access suppor
Page 1988 and 1989:
ARMv6 Differences CRn opc1 CRm opc2
Page 1990 and 1991:
ARMv6 Differences G.7.3 c0, ID supp
Page 1992 and 1993:
ARMv6 Differences When nU == 0 this
Page 1994 and 1995:
ARMv6 Differences Bit [17], TL TLB
Page 1996 and 1997:
ARMv6 Differences G.7.10 c7, Cache
Page 1998 and 1999:
ARMv6 Differences Accessing the Cac
Page 2000 and 2001:
ARMv6 Differences Blocking and non-
Page 2002 and 2003:
ARMv6 Differences R, bit [0] Block
Page 2004 and 2005:
ARMv6 Differences G.7.15 c9, TCM su
Page 2006 and 2007:
ARMv6 Differences Note Bit [1] was
Page 2008 and 2009:
ARMv6 Differences when the Security
Page 2010 and 2011:
ARMv6 Differences The format of a T
Page 2012 and 2013:
ARMv6 Differences For ARMv6, TLB lo
Page 2014 and 2015:
ARMv4 and ARMv5 Differences H.1 Int
Page 2016 and 2017:
ARMv4 and ARMv5 Differences H.2 App
Page 2018 and 2019:
ARMv4 and ARMv5 Differences H.3 App
Page 2020 and 2021:
ARMv4 and ARMv5 Differences Note Ta
Page 2022 and 2023:
ARMv4 and ARMv5 Differences H.3.4 M
Page 2024 and 2025:
ARMv4 and ARMv5 Differences H.4.1 A
Page 2026 and 2027:
ARMv4 and ARMv5 Differences Table H
Page 2028 and 2029:
ARMv4 and ARMv5 Differences Table H
Page 2030 and 2031:
ARMv4 and ARMv5 Differences H.5 Sys
Page 2032 and 2033:
ARMv4 and ARMv5 Differences The ARM
Page 2034 and 2035:
ARMv4 and ARMv5 Differences The Fas
Page 2036 and 2037:
ARMv4 and ARMv5 Differences First l
Page 2038 and 2039:
ARMv4 and ARMv5 Differences Second
Page 2040 and 2041:
ARMv4 and ARMv5 Differences H.6.4 P
Page 2042 and 2043:
ARMv4 and ARMv5 Differences Memory
Page 2044 and 2045:
ARMv4 and ARMv5 Differences H.7.1 O
Page 2046 and 2047:
ARMv4 and ARMv5 Differences H.7.3 c
Page 2048 and 2049:
ARMv4 and ARMv5 Differences For det
Page 2050 and 2051:
ARMv4 and ARMv5 Differences Excludi
Page 2052 and 2053:
ARMv4 and ARMv5 Differences Z, bit
Page 2054 and 2055:
ARMv4 and ARMv5 Differences In ARMv
Page 2056 and 2057:
ARMv4 and ARMv5 Differences c2, Mem
Page 2058 and 2059:
ARMv4 and ARMv5 Differences MRC p15
Page 2060 and 2061:
ARMv4 and ARMv5 Differences Encodin
Page 2062 and 2063:
ARMv4 and ARMv5 Differences Test an
Page 2064 and 2065:
ARMv4 and ARMv5 Differences H.7.11
Page 2066 and 2067:
ARMv4 and ARMv5 Differences Reading
Page 2068 and 2069:
ARMv4 and ARMv5 Differences The 32
Page 2070 and 2071:
ARMv4 and ARMv5 Differences Whether
Page 2072 and 2073:
ARMv4 and ARMv5 Differences The TLB
Page 2074 and 2075:
ARMv4 and ARMv5 Differences where a
Page 2076 and 2077:
ARMv4 and ARMv5 Differences AppxH-6
Page 2078 and 2079:
Pseudocode Definition I.1 Instructi
Page 2080 and 2081:
Pseudocode Definition I.2 Limitatio
Page 2082 and 2083:
Pseudocode Definition A special for
Page 2084 and 2085:
Pseudocode Definition After this de
Page 2086 and 2087:
Pseudocode Definition — a data ty
Page 2088 and 2089:
Pseudocode Definition I.5.3 Bitstri
Page 2090 and 2091:
Pseudocode Definition If x is a bit
Page 2092 and 2093:
Pseudocode Definition Square Root I
Page 2094 and 2095:
Pseudocode Definition UNPREDICTABLE
Page 2096 and 2097:
Pseudocode Definition repeat ... un
Page 2098 and 2099:
Pseudocode Definition I.7 Miscellan
Page 2100 and 2101:
Pseudocode Definition I.7.14 Coproc
Page 2102 and 2103:
Pseudocode Definition I.7.28 Memory
Page 2104 and 2105:
Pseudocode Index J.1 Pseudocode ope
Page 2106 and 2107:
Pseudocode Index Operator Meaning S
Page 2108 and 2109:
Pseudocode Index J.2 Pseudocode fun
Page 2110 and 2111:
Pseudocode Index CheckTLB() Check w
Page 2112 and 2113:
Pseudocode Index DecodeImmShift() D
Page 2114 and 2115:
Pseudocode Index FPRecipEstimate()
Page 2116 and 2117:
Pseudocode Index IsOnes() Test for
Page 2118 and 2119:
Pseudocode Index R[] Access the mai
Page 2120 and 2121:
Pseudocode Index TakeSMCException()
Page 2122 and 2123:
Pseudocode Index WRPMatch() Check w
Page 2124 and 2125:
Register Index K.1 Register index T
Page 2126 and 2127:
Register Index Register In a Descri
Page 2128 and 2129:
Page 2130 and 2131:
Page 2132 and 2133:
Page 2134 and 2135:
Page 2136 and 2137:
Page 2138 and 2139:
Page 2140 and 2141:
Page 2142 and 2143:
Page 2144 and 2145:
Page 2146 and 2147:
Glossary Atomicity Is a term that d
Page 2148 and 2149:
Glossary Conditional execution Mean
Page 2150 and 2151:
Glossary High vectors Are alternati
Page 2152 and 2153:
Glossary Physical address (PA) Iden
Page 2154 and 2155:
Glossary Round towards Zero (RZ) mo
Page 2156 and 2157:
Glossary Temporal locality Is the o
Page 2158:
Glossary Word Is a 32-bit data item
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