ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
VRECPE. , Encoded as Q = 1
VRECPE. , Encoded as Q = 0
where:
Instruction Details
See Standard assembler syntax fields on page A8-7. An ARM VRECPE instruction must be
unconditional.
The data types for the elements of the vectors. It must be one of:
U32 encoded as F = 0, size = 0b10
F32 encoded as F = 1, size = 0b10.
, The destination vector and the operand vector, for a quadword operation.
, The destination vector and the operand vector, for a doubleword operation.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDEnabled();
for r = 0 to regs-1
for e = 0 to elements-1
if floating_point then
Elem[D[d+r],e,esize] = FPRecipEstimate(Elem[D[m+r],e,esize]);
else
Elem[D[d+r],e,esize] = UnsignedRecipEstimate(Elem[D[m+r],e,esize]);
Exceptions
Undefined Instruction.
Floating-point exceptions: Input Denormal, Invalid Operation, Underflow, and Division by Zero.
Newton-Raphson iteration
For details of the operation performed and how it can be used in a Newton-Raphson iteration to calculate
the reciprocal of a number, see Reciprocal estimate and step on page A2-58.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-729