ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARMv6 Differences
Bit [17], TL TLB Lockdown Register access for support in CP15 c10 in the Non-secure address space.
For information on TLB lockdown support in ARMv6 see c10, VMSA TLB lockdown
support on page AppxG-53.
Bit [16], CL Cache Lockdown Register access for support in CP15 c9 in the Non-secure address space.
For information on cache lockdown support in ARMv6 see c9, Cache lockdown support on
page AppxG-45.
In all cases:
a value of 0 in the bit position specifies that the associated registers cannot be accessed in the
Non-secure address space
a value of 1 in the bit position specifies that the associated registers can be accessed in the Secure and
Non-secure address spaces.
Support of these additional bits and more details on how DMA support for TCMs, TLB lockdown, and cache
lockdown are inhibited in the Non-secure address space is IMPLEMENTATION DEFINED.
G.7.6 c2 and c3, VMSA memory protection and control registers
ARMv6 and ARMv7 provide the same CP15 support:
two Translation Table Base Registers, TTBR0 and TTBR1
a Translation Table Base Control Register, TTBCR
a Domain Access Control Register, DACR.
The translation table registers are defined in CP15 c2, Translation table support registers on page B3-113.
The Domain Access Control Register (DACR) is as defined in c3, Domain Access Control Register (DACR)
on page B3-119.
Note
When the Security Extensions are implemented, these registers are Banked registers.
G.7.7 c5 and c6, VMSA memory system support
The support in ARMv6 is the same as ARMv7 with the following exceptions:
Bit 12 of the data and instruction fault status registers is not defined in ARMv6. See c5, Data Fault
Status Register (DFSR) on page B3-121 and c5, Instruction Fault Status Register (IFSR) on
page B3-122.
The Auxiliary Data Fault Status Register (ADFSR) and the Auxiliary Instruction Fault Status
Register (AIFSR) are not defined in ARMv6. See c5, Auxiliary Data and Instruction Fault Status
Registers (ADFSR and AIFSR) on page B3-123.
The Access Flag faults shown in Table B3-11 on page B3-50 and Table B3-12 on page B3-51 are
only supported in ARMv6K.
AppxG-36 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B