ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Stalling of accesses to the DCC registers
In Stall mode and Fast mode, accesses to the DCC registers can stall:
Debug Registers Reference
The mechanism by which an access is stalled by the external debug interface must be defined by the
external debug interface. For details of how accesses are stalled by the recommended ARM Debug
Interface v5, see the ARM Debug Interface v5 Architecture Specification.
The mechanism by which an access is stalled by the memory-mapped interface must be defined by
the memory-mapped interface.
A stall is a side-effect of an access. If the debug logic is in a state where an access has no side-effects,
the access does not stall. For more information about debug logic states in which accesses have no
side effects see Permission summaries for memory-mapped and external debug interfaces on
page C6-45.
Note
When the selected DCC access mode is Stall mode or Fast mode, all accesses through the Extended CP14
interface are UNPREDICTABLE.
Restrictions on accesses to DBGITR, DBGDTRRXext and DBGDTRTXext
If an access is made when the OS Lock is set or when the Sticky Power-down status bit is set to 1, then:
the access generates an error response
register reads have no side-effects
register writes are ignored
the flags remain unchanged.
This applies both to accesses through the external debug interface and to accesses through the
memory-mapped interface.
If an access is made through the memory-mapped interface when the Software Lock is set then:
register reads have no side-effects
register writes are ignored
the flags remain unchanged.
For more information, see Permission summaries for memory-mapped and external debug interfaces on
page C6-45.
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