ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
The instruction is in the same 4KB block of memory (aligned to 4KB) from which an instruction has
previously been required by a simple sequential execution of the program with the MMU disabled,
or is in the 4KB block immediately following such a block.
Note
Software must ensure that instructions that will be executed when the MMU is disabled are located
within 4KB blocks of the address space that contain only memory which is tolerant to prefetching
and speculative accesses, and that the following 4KB blocks of the address space also contain only
memory which is tolerant to prefetching and speculative accesses.
Enabling or disabling the MMU effectively changes the translation tables that are in use. The
synchronization requirements that apply on changing translation tables also apply to enabling or
disabling the MMU. For more information, see Changing translation table attributes on page B3-21.
See also Requirements for instruction caches on page B3-23.
In addition, if the physical address of the code that enables or disables the MMU differs from its
MVA, instruction prefetching can cause complications. Therefore, ARM strongly recommends that
any code that enables or disables the MMU has identical virtual and physical addresses.
B3-6 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B