ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Events
Note
Normally, exception vector addresses must be word-aligned. However, when SCTLR.VE == 1, enabling
vectored interrupt support, the exception vector address for one or both of the IRQ and FIQ vectors might
not be word-aligned. Support for exception vector addresses that are not word-aligned is IMPLEMENTATION
DEFINED, see Vectored interrupt support on page B1-32.
If Monitor debug-mode is selected and enabled, and the vector is either the Prefetch Abort vector or the Data
Abort vector, the debug event is:
UNPREDICTABLE in v7 Debug
ignored in v6 Debug and v6.1 Debug.
Vector Catch debug events are synchronous. That is, the debug event acts like an exception that cancels the
instruction at the caught vector. When invasive debug is enabled and Monitor debug-mode is selected, if
Vector Catch debug events are permitted a Vector Catch debug event generates a Prefetch Abort exception.
For more information, see Generation of debug events on page C3-40.
Note
A Vector Catch debug event is taken only when the instruction is committed for execution and therefore
might not be taken if another exception occurs, see Debug event prioritization on page C3-43.
For more information, see Vector Catch Register (DBGVCR) on page C10-67.
Vector catch debug events and vectored interrupt support
The ARM architecture provides support for vectored interrupts, where an interrupt controller provides the
interrupt vector address directly to the processor. The mechanism for defining the vectors is
IMPLEMENTATION DEFINED. You enable the use of vectored interrupts by setting the SCTLR.VE bit to 1. For
more information see Vectored interrupt support on page B1-32.
Vectored interrupt support affects Vector Catch debug event generation for the IRQ and FIQ exception
vectors. These two vectors are described as the interrupt vectors. The details of Vector Catch debug event
generation on the interrupt vectors depend on whether the Security Extensions are implemented:
If the Security Extensions are not implemented
If the SCTRL.VE bit is set to 0, then the Local vector addresses for IRQ and FIQ
vector catch are determined by the exception base address.
If the SCTRL.VE bit is set to 1, then the Local vector address for an IRQ or FIQ
vector catch is the interrupt vector address supplied by the interrupt controller on
taking the interrupt.
C3-22 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B