ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Advanced SIMD and VFP Instruction Encoding
A7.8 8, 16, and 32-bit transfer between ARM core and extension registers
If T == 1 in the Thumb encoding or cond == 0b1111 in the ARM encoding, the instruction is UNDEFINED.
Otherwise, the allocation of encodings in this space is shown in Table A7-22. Other encodings in this space
are UNDEFINED.
These instructions are MRC and MCR instructions for coprocessors 10 and 11.
Thumb encoding
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 T 1 1 1 0 A L 1 0 1 C B 1
ARM encoding
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 1 1 1 0 A L 1 0 1 C B 1
L C A B Instruction See
Table A7-22 8-bit, 16-bit and 32-bit data transfer instructions
0 0 000 - Vector Move VMOV (between ARM core register and
single-precision register) on page A8-648
111 - Move to VFP Special Register from
ARM core register
VMSR on page A8-660
VMSR on page B6-29 (System level view)
0 1 0xx - Vector Move VMOV (ARM core register to scalar) on
page A8-644
1xx 0x Vector Duplicate VDUP (ARM core register) on page A8-594
1 0 000 - Vector Move VMOV (between ARM core register and
single-precision register) on page A8-648
111 - Move to ARM core register from VFP
Special Register
VMRS on page A8-658
VMRS on page B6-27 (System level view)
1 xxx - Vector Move VMOV (scalar to ARM core register) on
page A8-646
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A7-31