ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Registers Reference
Bit [21], IVA or Context ID comparison
This bit is set to 1 for a Context ID comparison.
This bit is UNK/SBZP for BRPs that do not support Context ID comparison. In
this case field values of 0b010 and 0b011 are not supported.
Bit [20], Unlinked or Linked comparison
This bit is set to 1 if this BRP is linked to another BRP to set a breakpoint that
requires both IVA and Context ID comparison.
For more information about IVA matching and mismatching see:
Byte address selection behavior on IVA match or mismatch on page C10-55
Breakpoint address range masking behavior, v7 Debug on page C3-9
IVA comparisons and instruction length on page C3-10.
The possible values of the DBGBVR meaning field are:
0b000 Unlinked Instruction Virtual Address match
Compare:
the byte address select bits, bits [8:5], and the associated
DBGBVR[31:2], against the IVA of the instruction
the security state control and privileged mode control bits,
bits [15:14,2:1], against the state of the processor.
Generate a Breakpoint debug event on a joint IVA match and state match.
DBGBCR[19:16] must be programmed to 0b0000, otherwise the generation of
Breakpoint debug events is UNPREDICTABLE.
0b001 Linked Instruction Virtual Address match
Compare:
the byte address select bits, bits [8:5], and the associated
DBGBVR[31:2], against the IVA of the instruction
the security state control and privileged mode control bits,
bits [15:14,2:1], against the state of the processor.
This BRP is linked with the BRP indicated by DBGBCR[19:16]. Generate a
Breakpoint debug event on a joint IVA match, Context ID match and state
match. For more information, see Linked comparisons on page C10-59.
0b010 Unlinked Context ID match
Compare:
the associated DBGBVR[31:0] against the Context ID in the
CONTEXTIDR
the security state control and privileged mode control bits,
bits [15:14,2:1], against the state of the processor.
This BRP is not linked with any other one. Generate a Breakpoint debug event
on a joint Context ID match and state match.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C10-51