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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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B3.5.1 The effect of the Security Extensions on the cache operations<br />

Virtual Memory System <strong>Architecture</strong> (VMSA)<br />

When the Security Extensions are implemented <strong>and</strong> each security state has its own physical address space,<br />

Table B3-3 shows the effect of the security state on the cache operations.<br />

Cache operation<br />

Instruction cache operations<br />

Security<br />

state<br />

Invalidate All Non-<br />

secure<br />

Table B3-3 Effect of the security state on the cache operations<br />

Targeted entry<br />

Invalidate All Secure All instruction cache lines<br />

Invalidate by MVA Either Base <strong>Architecture</strong>:<br />

Data or unified cache operations<br />

Invalidate, Clean, Clean<br />

<strong>and</strong> Invalidate by set/way<br />

Invalidate, Clean, Clean<br />

<strong>and</strong> Invalidate by set/way<br />

Invalidate, Clean, Clean<br />

<strong>and</strong> Invalidate by MVA<br />

Non-<br />

secure<br />

All instruction cache lines that contain entries that can be accessed<br />

from the Non-secure security state<br />

All Lines that match the specified MVA <strong>and</strong> the current ASID <strong>and</strong><br />

come from the same virtual address space as the current security<br />

state<br />

IVIPT extension: a<br />

All Lines that match the specified MVA <strong>and</strong> the current ASID <strong>and</strong><br />

come from the same physical address space as described in the<br />

translation tables<br />

Line specified by set/way provided that the entry comes from the<br />

Non-secure physical address space<br />

Secure Line specified by set/way regardless of the physical address space that<br />

the entry has come from<br />

Either All Lines that match the specified MVA <strong>and</strong> the current ASID <strong>and</strong><br />

come from the same physical address space, as described in the<br />

translation tables<br />

a. For more information about the IVIPT extension see Requirements for instruction caches on page B3-23.<br />

For locked entries <strong>and</strong> entries that might be locked, the behavior of cache maintenance operations described<br />

in The interaction of cache lockdown with cache maintenance on page B2-18 applies. This behavior is not<br />

affected by the Security Extensions.<br />

With an implementation that generates aborts if entries are locked or might be locked in the cache, if the use<br />

of lockdown aborts is enabled then these aborts can occur on any cache maintenance operation regardless<br />

of the Security Extensions.<br />

<strong>ARM</strong> DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. B3-27

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