ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Application Level Memory Model
Reverse halfword and sign-extend, for transforming signed 16-bit representations. See REVSH on
page A8-276.
Reverse packed halfwords in a register for transforming big- and little-endian 16-bit representations.
See REV16 on page A8-274.
A3.3.5 Endianness in Advanced SIMD
Advanced SIMD element load/store instructions transfer vectors of elements between memory and the
Advanced SIMD register bank. An instruction specifies both the length of the transfer and the size of the
data elements being transferred. This information is used by the processor to load and store data correctly
in both big-endian and little-endian systems.
Consider. for example, the instruction:
VLD1.16 {D0}, [R1]
This loads a 64-bit register with four 16-bit values. The four elements appear in the register in array order,
with the lowest indexed element fetched from the lowest address. The order of bytes in the elements depends
on the endianness configuration, as shown in Figure A3-1. Therefore, the order of the elements in the
registers is the same regardless of the endianness configuration. This means that Advanced SIMD code is
usually independent of endianness.
0 A[7:0]
1 A[15:8]
2 B[7:0]
3 B[15:8]
4 C[7:0]
5 C[15:8]
6 D[7:0]
7 D[15:8]
Memory system with
Little endian addressing (LE)
64-bit register containing four 16-bit elements
D[15:8] D[7:0] C[15:8] C[7:0] B[15:8] B[7:0] A[15:8] A[7:0]
VLD1.16 {D0}, [R1]
VLD1.16 {D0}, [R1]
Figure A3-1 Advanced SIMD byte order example
The Advanced SIMD extension supports Little-Endian (LE) and Big-Endian (BE) models.
A[15:8]
A[7:0]
B[15:8]
B[7:0]
C[15:8]
C[7:0]
D[15:8]
D[7:0]
Memory system with
Big endian addressing (BE)
For information about the alignment of Advanced SIMD instructions see Unaligned data access on
page A3-5.
A3-10 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B
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