ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
AND{S} {,} , {,}
where:
Instruction Details
S If S is present, the instruction updates the flags. Otherwise, the flags are not updated.
See Standard assembler syntax fields on page A8-7.
The destination register.
The first operand register.
The register that is optionally shifted and used as the second operand.
The shift to apply to the value read from . If present, encoding T1 is not permitted. If
absent, no shift is applied and all encodings are permitted. Shifts applied to a register on
page A8-10 describes the shifts and how they are encoded.
In Thumb assembly:
outside an IT block, if ANDS ,, has and both in the range R0-R7, it is assembled
using encoding T1 as though ANDS , had been written
inside an IT block, if AND ,, has and both in the range R0-R7, it is
assembled using encoding T1 as though AND , had been written.
To prevent either of these happening, use the .W qualifier.
The pre-UAL syntax ANDS is equivalent to ANDS.
Operation
if ConditionPassed() then
EncodingSpecificOperations();
(shifted, carry) = Shift_C(R[m], shift_t, shift_n, APSR.C);
result = R[n] AND shifted;
if d == 15 then // Can only occur for ARM encoding
ALUWritePC(result); // setflags is always FALSE here
else
R[d] = result;
if setflags then
APSR.N = result;
APSR.Z = IsZeroBit(result);
APSR.C = carry;
// APSR.V unchanged
Exceptions
None.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-37