ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

C, bit [0], ARMv7-A base architecture
Virtual Memory System Architecture (VMSA)
See the definition given for the TTBR0 in c2, Translation Table Base Register 0 (TTBR0)
on page B3-113.
Accessing the TTBR1 register
To access the TTBR1 register you read or write the CP15 registers with set to 0, set to c2,
set to c0, and set to 1. For example:
MRC p15,0,,c2,c0,1 ; Read CP15 Translation Table Base Register 1
MCR p15,0,,c2,c0,1 ; Write CP15 Translation Table Base Register 1
c2, Translation Table Base Control Register (TTBCR)
The Translation Table Base Control Register, TTBCR, determines which of the Translation Table Base
Registers, TTBR0 or TTBR1, defines the base address for the translation table walk that is required when
an MVA is not found in the TLB.
The TTBCR:
Is a 32-bit read/write register.
Is accessible only in privileged modes
Has a defined reset value of 0. When the Security Extensions are implemented, this reset value
applies only to the Secure copy of the register, and software must program the Non-secure copy of
the register with the required value.
When the Security Extensions are implemented:
— is a Banked register.
— has write access to the Secure copy of the register disabled when the CP15SDISABLE signal
is asserted HIGH.
When the Security Extensions are not implemented, the format of the TTBCR is:
31 3 2 0
When the Security Extensions are implemented, the format of the TTBCR is:
Bits [31:6, 3] UNK/SBZP.
UNK/SBZP
31 6 5 4 3 2 0
UNK/SBZP
PD1, bit [5], when Security Extensions are implemented
Translation table walk Disable bit for TTBR1. This bit controls whether a translation table
walk is performed on a TLB miss when TTBR1 is used:
0 If a TLB miss occurs when TTBR1 is used a translation table walk is performed.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B3-117
PD1
PD0
(0)
N
N