ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Protected Memory System Architecture (PMSA)
For details of the reset values of these registers see the register descriptions.
After a reset, software must not rely on the value of any read/write register not included in this list.
B4.6.3 Changes to CP15 registers and the memory order model
All changes to CP15 registers that appear in program order after any explicit memory operations are
guaranteed not to affect those memory operations.
Any change to CP15 registers is guaranteed to be visible to subsequent instructions only after one of:
the execution of an ISB instruction
the taking of an exception
the return from an exception.
To guarantee the visibility of changes to some CP15 registers, additional operations might be required, on
a case by case basis, before the ISB instruction, exception or return from exception. These cases are
identified specifically in the definition of the registers.
However, for CP15 register accesses, all MRC and MCR instructions to the same register using the same register
number appear to occur in program order relative to each other without context synchronization.
Where a change to the CP15 registers that is not yet guaranteed to be visible has an effect on exception
processing, the following rule applies:
When it is determined that an exception must be taken, any change of state held in CP15 registers
involved in the triggering of the exception and that affects the processing of the exception is
guaranteed to take effect before the exception is taken.
Therefore, in the following example, where initially A=1 and V=0, the LDR might or might not take a Data
Abort exception due to the unaligned access, but if an exception occurs, the vector used is affected by the V
bit:
MCR p15, R0, c1, c0, 0 ; clears the A bit and sets the V bit
LDR R2, [R3] ; unaligned load.
B4-28 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B