ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Fast Context Switch Extension (FCSE)
Each process is compiled to use the address range 0x00000000 to 0x01FFFFFF. When referring to its own
instructions and data, therefore, the program generates VAs whose top seven bits are all zero. The resulting
MVAs have their top seven bits replaced by FCSEIDR.PID, and so lie in the process block of the current
process.
The program can also generate VAs whose top seven bits are not all zero. When this happens, the MVA is
equal to the VA. This enables the program to address the process block of another process, provided the
other process does not have process ID 0. Provided access permissions are set correctly, this can be used for
inter-process communication.
Note
ARM recommends that only process IDs 1 and above are used for general-purpose processes, because the
process with process ID 0 cannot be communicated with in this fashion.
Use of the FCSE therefore reduces the cost of a process swap to:
The cost of a write of the FCSEIDR.PID.
The cost of changing access permissions if they need changing for the new process. In an
MMU-based system, this might involve changing the translation table entries individually, or
pointing to a new translation table by changing one or more of TTBR0, TTBR1, and TTBCR. Any
change to the translation tables is likely to involve invalidation of the TLB entries affected. However,
this is usually significantly cheaper than the cache flush that would be required without the FCSE.
Also, in some cases, changes to the translation table, and the associated explicit TLB management,
can be avoided by the use of domains. This reduces the cost to that of a write to the Domain Access
Control Register, see Domains on page B3-31.
The FCSE is deprecated. The use of cache, branch predictor and TLB operations with MVA based addresses
that, as a result of the Multiprocessing Extensions, would affect other processors as described in section 3.2
is UNPREDICTABLE if FCSEIDR.PID is not zero.
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