ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Common VFP Subarchitecture Specification
— If it is a not a VFP access permission fault, determine the iteration count
from FPSCR.LEN, and set the return address to the instruction following
the bounced instruction. Then continue processing from step 2.
FPEXC.EX == 0, FPEXC.DEX == 1
The bounced instruction was executed as a valid floating-point operation, and it bounced
because of an exceptional condition.
The exception-generating instruction is the instruction that bounced.
The iteration count is determined from either FPSCR.LEN or FPEXC.VECITR,
depending on the value of FPEXC.VV:
if FPEXC.VV is set to 0, the iteration count is determined from FPSCR.LEN
if FPEXC.VV is set to 1, the iteration count is determined from FPEXC.VECITR.
Clear the FPEXC.DEX bit to 0, and set the return address to the instruction following the
bounced instruction.
Continue processing from step 2.
FPEXC.EX == 1
The VFP bounce resulted from an asynchronous exception.
Collect information about the exceptional instruction, and any other instructions that are
to be executed by support code. Clear the exceptional condition. For each instruction the
data collected include the instruction encoding and the number of vector iterations.
This involves:
Read the FPINST Register to find the exception-generating instruction.
Read the FPEXC.VECITR field to find the remaining iteration count for this
instruction.
Check FPEXC.FP2V. If it is set to 1 there is a bypassed instruction:
— Read the FPINST2 Register to find the bypassed instruction
— Clear the FPEXC.EX and FPEXC.FP2V bits to 0.
— Read the FPSCR.LEN field to find the iteration count for the bypassed
instruction.
The FPSCR can be read-only when FPEXC.EX == 0.
Otherwise there is no bypassed instruction:
— Clear FPEXC.EX to 0.
FPEXC.EX == 0 indicates there is no subarchitecture state to context switch.
Set the return address to re-execute the trigger instruction.
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