ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Registers Reference
The format of the PMCR is:
31 24 23 16 15 11 10 6 5 4 3 2 1 0
IMP IDCODE N UNK/SBZP DP X D C P E
IMP, bits [31:24]
Implementer code. This is a read-only field with an IMPLEMENTATION DEFINED value.
The Implementer codes are allocated by ARM. Values have the same interpretation as bits
[31:24] of the CP15 Main ID Register, see:
c0, Main ID Register (MIDR) on page B3-81 for a VMSA implementation
c0, Main ID Register (MIDR) on page B4-32 for a PMSA implementation.
IDCODE, bits [23:16]
Identification code. This is a read-only field with an IMPLEMENTATION DEFINED value.
Each implementer must maintain a list of identification codes that is specific to the
implementer. A specific implementation is identified by the combination of the implementer
code and the identification code.
N, bits [15:11]
Number of event counters. This is a read-only field with an IMPLEMENTATION DEFINED value
that indicates the number of counters implemented.
The value of this field is the number of counters implemented, from 0b00000 for no counters
to 0b11111 for 31 counters.
An implementation can implement only the Clock Counter (PMCCNTR) Register. This is
indicated by a value of 0b00000 for the N field.
Bits [10:6] Reserved, UNK/SBZP.
DP, bit [5] Disable PMCCNTR when prohibited. The possible values of this bit are:
0 Count is enabled in prohibited regions
1 Count is disabled in prohibited regions.
Prohibited regions are defined as regions where event counting would be prohibited. For
example, if non-invasive debug is disabled in all Secure modes, the Secure state is a
prohibited region. For details of non-invasive debug authentication see Chapter C7
Non-invasive Debug Authentication.
Note
This bit permits a Non-secure process to discard cycle counts that might be accumulated
during periods when the other counts are prohibited because of security prohibitions. It is
not a control to enhance security. The function of this bit is to avoid corruption of the count.
See also Interaction with Security Extensions on page C9-7.
This is a read/write bit. Its core logic reset value is 0.
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