ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
VQSHR{U}N. , , #
where:
Instruction Details
U If present, specifies that the results are unsigned, although the operands are signed.
See Standard assembler syntax fields on page A8-7. An ARM VQSHRN or VQSHRUN instruction
must be unconditional.
The data type for the elements of the vectors. It must be one of:
S encoded as:
U = 0, op = 1, if U is absent
U = 1, op = 0, if U is present
U encoded as U = 1, op = 1. Not available for VQSHRUN.
The data size for the elements of the vectors. It must be one of:
16 Encoded as imm6 = ’001’. (8 – ) is encoded in imm6.
32 Encoded as imm6 = ’01’. (16 – ) is encoded in imm6.
64 Encoded as imm6 = ’1’. (32 – ) is encoded in imm6.
, The destination vector, and the operand vector.
The immediate value, in the range 1 to /2. See the description of for how
is encoded.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDEnabled();
for e = 0 to elements-1
operand = Int(Elem[Q[m>>1],e,2*esize], src_unsigned);
(result, sat) = SatQ(operand >> shift_amount, esize, dest_unsigned);
Elem[D[d],e,esize] = result;
if sat then FPSCR.QC = ‘1’;
Exceptions
Undefined Instruction.
Pseudo-instructions
VQSHRN.I , , #0 is a synonym for VQMOVN.I ,
VQSHRUN.I , , #0 is a synonym for VQMOVUN.I ,
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-723