ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
VSTR{.64} , [{, #+/-}] Encoding T1 / A1
VSTR{.32} , [{, #+/-}] Encoding T2 / A2
where:
See Standard assembler syntax fields on page A8-7.
.32, .64 Optional data size specifiers.
The source register for a doubleword store.
The source register for a singleword store.
Instruction Details
The base register. The SP can be used. In the ARM instruction set the PC can be used.
However, use of the PC is deprecated.
+/- Is + or omitted if the immediate offset is to be added to the base register value (add == TRUE),
or – if it is to be subtracted (add == FALSE). #0 and #-0 generate different instructions.
The immediate offset used to form the address. Values are multiples of 4 in the range
0-1020. can be omitted, meaning an offset of +0.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckVFPEnabled(TRUE); NullCheckIfThumbEE(n);
address = if add then (R[n] + imm32) else (R[n] - imm32);
if single_reg then
MemA[address,4] = S[d];
else
// Store as two word-aligned words in the correct order for current endianness.
MemA[address,4] = if BigEndian() then D[d] else D[d];
MemA[address+4,4] = if BigEndian() then D[d] else D[d];
Exceptions
Undefined Instruction, Data Abort.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-787