ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
NS, bit [0] Non Secure bit. Except when the processor is in Monitor mode, this bit determines the
security state of the processor. Table B3-27 shows the security settings:
For more information, see Changing from Secure to Non-secure state on page B1-27.
The value of the NS bit also affects the accessibility of the Banked CP15 registers in Monitor
mode, see Access to registers in Monitor mode on page B3-77.
Unless the processor is in Debug state, when an exception occurs in Monitor mode the
hardware sets the NS bit to 0.
Whenever the processor changes security state, the monitor code can change the value of the EA, FIQ and
IQ bits. This means that the behavior of IRQ, FIQ and External Abort exceptions can be different in each
security state.
Accessing the SCR
SCR.NS
To access the SCR you read or write the CP15 registers with set to 0, set to c1, set to c1,
and set to 0. For example:
MRC p15,0,,c1,c1,0 ; Read CP15 Secure Configuration Register
MCR p15,0,,c1,c1,0 ; Write CP15 Secure Configuration Register
B3.12.21 c1, Secure Debug Enable Register (SDER)
The Secure Debug Enable Register, SDER, is part of the Security Extensions.
The SDER controls invasive and non-invasive debug in Secure User mode.
The SDER is:
present only when the Security Extensions are implemented
a 32-bit read/write register
a Restricted access register, meaning it exists only in the Secure state
accessible in Secure privileged modes only.
Table B3-27 Processor security state
Processor mode, from CPSR.M bits
Monitor mode All modes except Monitor mode
0 Secure state Secure state
1 Secure state Non-secure state
B3-108 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B