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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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The System Level Programmers’ Model<br />

If SPSR.J <strong>and</strong> SPSR.T are not both 0, indicating that the exception occurred in Thumb state or<br />

ThumbEE state, use an exception return instruction with a subtraction of 2.<br />

For more information, see Exception return on page B1-38.<br />

Note<br />

Undefined Instruction exceptions cannot occur in Jazelle state<br />

If h<strong>and</strong>ling the Undefined Instruction exception requires instruction emulation, followed by return to<br />

the next instruction after the instruction that caused the exception, the instruction emulator must use<br />

the instruction length to calculate the correct return address, <strong>and</strong> to calculate the updated values of<br />

the IT bits if necessary.<br />

Conditional execution of undefined instructions<br />

The conditional execution rules described in Conditional execution on page A8-8 apply to all instructions.<br />

This includes UNDEFINED instructions <strong>and</strong> other instructions that would cause entry to the Undefined<br />

Instruction exception.<br />

If such an instruction fails its condition check, the behavior depends on the architecture profile <strong>and</strong> the<br />

potential cause of entry to the Undefined Instruction exception, as follows:<br />

In the <strong>ARM</strong>v7-A profile:<br />

— If the potential cause is the execution of the instruction itself <strong>and</strong> depends on data values the<br />

instruction reads, the instruction executes as a NOP <strong>and</strong> does not cause an Undefined<br />

Instruction exception.<br />

— If the potential cause is the execution of an earlier coprocessor instruction, or the execution of<br />

the instruction itself but does not depend on data values the instruction reads, it is<br />

IMPLEMENTATION DEFINED whether the instruction executes as a NOP or causes an Undefined<br />

Instruction exception.<br />

An implementation must h<strong>and</strong>le all such cases in the same way.<br />

In the <strong>ARM</strong>v7-R profile, the instruction executes as a NOP <strong>and</strong> does not cause an Undefined<br />

Instruction exception.<br />

Note<br />

Before <strong>ARM</strong>v7, all implementations executed any instruction that failed its condition check as a NOP, even<br />

if it would otherwise have caused an Undefined Instruction exception. Undefined Instruction h<strong>and</strong>lers<br />

written for these implementations might assume without checking that the undefined instruction passed its<br />

condition check. Such Undefined Instruction h<strong>and</strong>lers are likely to need rewriting, to check the condition is<br />

passed, before they function correctly on all <strong>ARM</strong>v7-A implementations.<br />

<strong>ARM</strong> DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. B1-51

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