ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.408 VTST
Vector Test Bits takes each element in a vector, and bitwise ANDs it with the corresponding element of a
second vector. If the result is not zero, the corresponding element in the destination vector is set to all ones.
Otherwise, it is set to all zeros.
The operand vector elements can be any one of:
8-bit, 16-bit, or 32-bit fields.
The result vector elements are bitfields the same size as the operand vector elements.
Encoding T1 / A1 Advanced SIMD
VTST. , ,
VTST. , ,
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 1 1 1 0 D size Vn Vd 1 0 0 0 N Q M 1 Vm
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 0 0 D size Vn Vd 1 0 0 0 N Q M 1 Vm
if Q == ‘1’ && (Vd == ‘1’ || Vn == ‘1’ || Vm == ‘1’) then UNDEFINED;
if size == ‘11’ then UNDEFINED;
esize = 8