ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARMv6 Differences
G.3 Application level memory support
Memory support covers address alignment, endian support, semaphore support, memory order model,
caches, and write buffers. The following sections give an application level description of ARMv6 memory
support:
Alignment
Endian support on page AppxG-7
Semaphore support on page AppxG-8
Memory model and memory ordering on page AppxG-8.
G.3.1 Alignment
ARMv6 supports:
a legacy alignment configuration compatible with ARMv5
the ARMv7 alignment configuration that supports unaligned loads and stores of 16-bit halfwords and
32-bit words.
The alignment configuration is controlled by the SCTLR.U bit, see c1, System Control Register (SCTLR) on
page AppxG-34:
SCTLR.U == 0
ARMv5 compatible alignment support, see Alignment on page AppxH-6, except for the
LDRD and STRD instructions. LDRD and STRD must be doubleword-aligned, otherwise:
if SCTLR.A == 0, the instruction is UNPREDICTABLE
if SCTLR.A == 1, the instruction causes an Alignment fault.
Note
The behavior of LDRD and STRD with SCTLR.A == 0 is compatible with ARMv5. When
SCTLR.A == 1, whether the alignment check is for word or doubleword alignment is:
IMPLEMENTATION DEFINED in ARMv5
required to be for doubleword alignment in ARMv6.
SCTLR.U == 1
Unaligned access support for loads and stores of single 16-bit halfwords and 32-bit words,
using the LDR, LDRH, LDRHT, LDRSH, LDRSHT, LDRT, STRH, STRHT, STR, and STRT instructions. Some
of these instructions were introduced in ARMv6T2.
The following requirements also apply:
LDREX and STREX exclusive access instructions must be word-aligned, otherwise the
instruction generates an abort.
In ARMv6K, an abort is generated if:
— an LDREXH or STREXH exclusive access instruction is not halfword-aligned
— an LDREXD or STREXD exclusive access instruction is not doubleword-aligned.
AppxG-6 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B