ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Register Interfaces
Debug Software Enable
Note
An external debugger can use the Debug Software Enable function to prevent modification
of the debug registers by a debug monitor or other software running on the system. The
Debug Software Enable is a required function of the Debug Access Port, and is implemented
as part of the ARM Debug Interface v5. For more information see the ARM Debug Interface
v5 Architecture Specification.
See also DBGSWENABLE on page AppxA-11.
The states of the Software Lock and the OS Lock are held in the debug power domain, and the Debug
Software Enable is in the Debug Access Port. Therefore, these locks are unaffected by the core power
domain powering down. Also, all of these locks are set to their reset values only on reset of the debug
power domain, that is. on a PRESETDBGn or nSYSPORESET reset.
On SinglePower systems, the Software Lock and OS Lock are lost over a power-down. It is
IMPLEMENTATION DEFINED whether the single processor power-domain also includes the Debug
Access Port, and therefore also whether the Debug Software Enable is lost over a power-down.
C6.5.3 Permissions in relation to power-down
Accesses cannot be made through the coprocessor interface when the core power domain is powered down.
Access to registers in the core power domain is not possible when the domain is powered down, and accesses
return an error response.
Note
Returning this error response, rather than simply ignoring writes, means that the debugger and the debug
monitor detect the debug session interruption as soon as it occurs. This makes re-starting the session, after
power-up, considerably easier.
When the core power domain powers down, the Sticky Power-down status bit, bit [1] of the Device
Power-down and Reset Status Register, is set to 1. This bit remains set to 1 until it is cleared to 0 by a read
of this register after the core power domain has powered up. If the register is read while the core power
domain is still powered down, the bit remains set to 1. When this bit is 1 the behavior is as if the core power
domain is powered down, meaning the processor ignores accesses to registers inside the core power domain
and the system returns an error. This applies whether the register is accessed through the Extended CP14
interface, the memory-mapped interface, or the external debug interface.
This behavior is useful because when the external debugger tries to access a register whose contents might
have been lost by a power-down, it gets the same response regardless of whether the core power domain is
currently powered down or has powered back up. This means that, if the external debugger does not access
the external debug interface during the window where the core power domain is powered down, the
processor still reports the occurrence of the power-down event.
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