ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
B3.12.22 c1, Non-Secure Access Control Register (NSACR)
The Non-Secure Access Control Register, NSACR, is part of the Security Extensions.
The NSACR defines the Non-secure access permissions to the coprocessors CP0 to CP13. Additional
IMPLEMENTATION DEFINED bits in the register can be used to define Non-secure access permissions for
IMPLEMENTATION DEFINED functionality.
The NSACR is:
Present only when the Security Extensions are implemented.
A 32-bit register
A Restricted access register. NSACR exists only in the Secure state, but can be read from Non-secure
state.
Accessible only in privileged modes, with access rights that depend on the mode and security state:
— the NSACR is read/write in Secure privileged modes
— the NSACR is read-only in Non-secure privileged modes.
The format of the NSACR is:
31 20 19 18 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits [31:20]
UNK/SBZP
RFR
NSASEDIS
Reserved. UNK/SBZP.
IMP
cp13 - - -
cp0
NSD32DIS Coprocessor Non-secure access enables,
cp13 to cp0, see text
RFR, bit [19] Reserve FIQ Registers:
0 FIQ mode and the FIQ banked registers are accessible in Secure and Non-secure
security states.
1 FIQ mode and the FIQ banked registers are accessible in the Secure security
state only. Any attempt to access any FIQ Banked register or to enter an FIQ
mode when in the Non-secure security states is UNPREDICTABLE.
This bit resets to 0. On some implementations this bit cannot be set to 1.
If NSACR.RFR == 1 when SCR.FIQ == 0, instruction execution is UNPREDICTABLE in
Non-secure security state.
Bits [18:16] IMPLEMENTATION DEFINED.
These bits can be used to define the Non-secure access to IMPLEMENTATION DEFINED
features.
B3-110 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B