ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Translation flow for a Small page
Virtual Memory System Architecture (VMSA)
Figure B3-6 shows the virtual to physical addresses translation for a Small page. For details of the access
control fields in the first-level descriptor see the Page table entry in Table B3-1 on page B3-8. For details of
the access control fields in the second-level descriptor see the Small page entry in Table B3-2 on
page B3-10.
Translation Table
Base Register
MVA
PA[31:0] of
first-level descriptor
PA[39:32] = 0x00
First-level
read
First-level
descriptor
PA[31:0] of
second-level descriptor
PA[39:32] = 0x00
Second-level
descriptor
31 14-N 13-N
Translation base SBZ
31 32-N 31-N
20 19
31 14-N 13-N 2 1
Translation base
First-level
table index
First-level
table index
Figure B3-6 Small page address translation
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B3-19
0
Second-level
table index
0
0 0
12 11
31 10 9
21
Page table base address
31 10 9
21
Second-level
read
Page table base address
31
31
Access
control fields
Second-level
table index
Small page base address
12 11
12 11
0
0 1
0
0 0
Page index
Access
control fields
PA[31:0]
PA[39:32] = 0x00
Small page base address Page index
For a translation based on TTBR0, N is the value of TTBCR.N
For a translation based on TTBR1, N is 0
‡ This field is absent if N==0
‡
1
0
21 0
0