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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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C4.1.2 Debug exception on Watchpoint debug event<br />

Debug Exceptions<br />

If the cause of the debug exception is a Watchpoint debug event, the processor performs the following<br />

actions:<br />

Sets the DBGDSCR.MOE bits either to Asynchronous Watchpoint Occurred or to Synchronous<br />

Watchpoint Occurred.<br />

Sets the DFSR, DFAR, <strong>and</strong> DBGWFAR as described in Effects of debug exceptions on CP15 registers<br />

<strong>and</strong> the DBGWFAR on page C4-4.<br />

Generates a precise Data Abort exception, see Data Abort exception on page B1-55.<br />

For more information, see Synchronous <strong>and</strong> Asynchronous Watchpoint debug events on page C3-18.<br />

The Data Abort h<strong>and</strong>ler is responsible for checking the DFSR bits to find out whether the exception entry<br />

was caused by a debug exception. If it was, typically the h<strong>and</strong>ler branches to the debug monitor:<br />

The DBGWFAR indicates the address of the instruction that caused the Watchpoint debug event. see<br />

Watchpoint Fault Address Register (DBGWFAR) on page C10-28.<br />

LR_abt holds the address of (instruction to restart at + 8). If the watchpoint is synchronous, the<br />

instruction to restart at is the instruction that triggered the watchpoint.<br />

<strong>ARM</strong> DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. C4-3

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