ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Performance Monitors
C9.4 Behavior on overflow
On counter overflow:
An overflow status flag is set to 1. See c9, Overflow Flag Status Register (PMOVSR) on
page C10-110.
An interrupt request is generated if the processor is configured to generate counter overflow
interrupts. For details see c9, Interrupt Enable Set Register (PMINTENSET) on page C10-118 and
c9, Interrupt Enable Clear Register (PMINTENCLR) on page C10-119.
The counter wraps to zero and continues counting events. Counting continues as long as the counters
are enabled, regardless of any overflows.
The counter always resets to zero and overflows after 32 bits of increment. To enable a more frequent
generation of interrupt requests, the counters can be written to. For example, an interrupt handler might reset
the overflowed counter to 0xFFFF0000 to generate another overflow interrupt after 16 bits of increment.
Note
The mechanism by which an interrupt request from the performance monitors generates an FIQ or IRQ
exception is IMPLEMENTATION DEFINED.
The interrupt handler for the counter interrupt must cancel the interrupt by clearing the overflow flag.
C9-6 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B