ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARMv4 and ARMv5 Differences
access permission register support that provides AP7[1:0] to AP0[1:0] 2-bit permission fields, an AP
bitfield for each region
optional extended access permission register support for 4-bit AP fields
region registers providing a base address, size field, and an enable bit for each region.
For details of the PMSA support in CP15 see c2, c3, c5, and c6, PMSA support on page AppxH-43.
The C and B bits are configured according to the type of memory that is to be accessed. For more
information, see Memory type support on page AppxH-10. Table H-10 defines the standard AP bit behavior.
Some implementations also include support for read-only access permission. Table H-11 defines the
extended AP bit behavior.
AP[3:0]
AP[1:0]
Privileged
permissions
Table H-10 PMSA access permissions in ARMv4 and ARMv5
User
permissions
Description
00 No access No access All accesses generate Permission faults
01 Read/write No access Privileged access only
10 Read/write Read-only Writes in User mode generate Permission faults
11 Read/write Read/write Full access
Privileged
permissions
Table H-11 PMSA extended access permissions in ARMv4 and ARMv5
User
permissions
Description
0000 No access No access All accesses generate a Permission fault
0001 Read/write No access Privileged access only
0010 Read/write Read-only Writes in User mode generate a Permission fault
0011 Read/write Read/write Full access
0100 UNPREDICTABLE UNPREDICTABLE -
0101 Read-only No access Privileged read-only access
0110 Read-only Read-only Read-only access
0111 UNPREDICTABLE UNPREDICTABLE -
1xxx UNPREDICTABLE UNPREDICTABLE -
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. AppxH-29