ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Square root, bits [23:20]
Divide, bits [19:16]
The CPUID Identification Scheme
Indicates the hardware support for VFP square root operations. Permitted values are:
0b0000 Not supported in hardware.
0b0001 Supported.
Note
the FSQRTS instruction also requires the single-precision VFP attribute, bits [7:4]
the FSQRTD instruction also requires the double-precision VFP attribute, bits [11:8].
Indicates the hardware support for VFP divide operations. Permitted values are:
0b0000 Not supported in hardware.
0b0001 Supported.
Note
VFP exception trapping, bits [15:12]
the FDIVS instruction also requires the single-precision VFP attribute, bits [7:4]
the FDIVD instruction also requires the double-precision VFP attribute, bits [11:8].
Indicates whether the VFP hardware implementation supports exception trapping.
Permitted values are:
0b0000 Not supported. This is the value for VFPv3.
0b0001 Supported by the hardware. This is the value for VFPv3U, and for VFPv2.
When exception trapping is supported, support code is needed to handle the
trapped exceptions.
Note
This value does not indicate that trapped exception handling is available.
Because trapped exception handling requires support code, only the support
code can provide this information.
Double-precision, bits [11:8]
Indicates the hardware support for VFP double-precision operations. Permitted values are:
0b0000 Not supported in hardware.
0b0001 Supported, VFPv2.
0b0010 Supported, VFPv3.
VFPv3 adds an instruction to load a double-precision floating-point constant,
and conversions between double-precision and fixed-point values.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B5-37