ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Registers Reference
C10.9.11 c9, Interrupt Enable Set Register (PMINTENSET)
The Interrupt Enable Set Register, PMINTENSET, enables the generation of interrupt requests on overflows
from:
the Cycle Count Register, PMCCNTR
each implemented event counter, PMNx.
Reading the PMINTENSET Register shows which overflow interrupts are enabled. Counter overflow
interrupts must be disabled using the PMINTENCLR Register, see c9, Interrupt Enable Clear Register
(PMINTENCLR) on page C10-119.
The PMINTENSET Register is:
A 32-bit read/write CP15 register:
— reading the register shows which overflow interrupts are enabled
— writing a 1 to a bit of the register enables the corresponding overflow interrupt
— writing a 0 to a bit of the register has no effect.
Accessible only in privileged modes.
The instructions that access the PMINTENSET Register are always UNDEFINED in User mode, even
if the PMUSERENR.EN flag is set to 1, see c9, User Enable Register (PMUSERENR) on
page C10-117.
When the Security Extensions are implemented, a Common register.
Accessed using an MRC or MCR command with set to c9, set to 0, set to c14, and
set to 1.
The format of the PMINTENSET Register is:
31 30 N N-1 0
C RAZ/WI Event counter overflow interrupt enable bits, Px, for x = 0 to (N-1)
Note
In the description of the PMINTENSET Register, N and x have the meanings used in the description of the
PMCNTENSET Register, see c9, Count Enable Set Register (PMCNTENSET) on page C10-108.
C, bit [31] PMCCNTR overflow interrupt enable bit.
See Table C10-28 on page C10-119 for the behavior of this bit on reads and writes.
Bits [30:N] RAZ/WI.
Px, bit [x], for x = 0 to (N-1)
Event counter x, PMNx, overflow interrupt enable bit.
C10-118 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B