ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Application Level Memory Model
In addition, any branches that appear in program order after the ISB instruction are written into the branch
prediction logic with the context that is visible after the ISB instruction. This is needed to ensure correct
execution of the instruction stream.
Any context altering operations appearing in program order after the ISB instruction only take effect after
the ISB has been executed.
For details of the ISB instruction in the Thumb and ARM instruction sets see ISB on page A8-102.
Pseudocode details of memory barriers
The following types define the required shareability domains and required access types used as arguments
for DMB and DSB instructions:
enumeration MBReqDomain {MBReqDomain_FullSystem,
MBReqDomain_OuterShareable,
MBReqDomain_InnerShareable,
MBReqDomain_Nonshareable};
enumeration MBReqTypes {MBReqTypes_All, MBReqTypes_Writes};
The following procedures perform the memory barriers:
DataMemoryBarrier(MBReqDomain domain, MBReqTypes types)
DataSynchronizationBarrier(MBReqDomain domain, MBReqTypes types)
InstructionSynchronizationBarrier()
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