05.02.2013 Views

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

SHOW MORE
SHOW LESS

Create successful ePaper yourself

Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.

F.2 Vector length <strong>and</strong> stride control<br />

VFP Vector Operation Support<br />

The FPSCR.LEN field, bits [18:16], controls the vector length for VFP instructions that operate on short<br />

vectors, that is, how many registers are in a vector oper<strong>and</strong>. Similarly, the FPSCR.STRIDE field,<br />

bits [21:20], controls the vector stride, that is, how far apart the registers in a vector lie in the register bank.<br />

For information about the FPSCR see Floating-point Status <strong>and</strong> Control Register (FPSCR) on page A2-28.<br />

The permitted combinations of LEN <strong>and</strong> STRIDE are shown in Table F-1. All other combinations of LEN<br />

<strong>and</strong> STRIDE produce UNPREDICTABLE results.<br />

The combination LEN == 0b000, STRIDE == 0b00 is called scalar mode. When it is in effect, all arithmetic<br />

instructions specify scalar operations. Otherwise, most arithmetic instructions specify a scalar operation if<br />

their destination is in the range:<br />

S0-S7 for a single-precision operation<br />

D0-D3 or D16-D19 for a double-precision operation.<br />

The full rules used to determine which oper<strong>and</strong>s are vectors <strong>and</strong> full details of how vector oper<strong>and</strong>s are<br />

specified can be found in VFP instruction type selection on page AppxF-7.<br />

The rules for vector oper<strong>and</strong>s do not permit the same register to appear twice or more in a vector. The<br />

permitted LEN <strong>and</strong> STRIDE combinations listed in Table F-1 never cause this to happen for<br />

single-precision instructions, so single-precision scalar <strong>and</strong> vector instructions can be used with all of these<br />

LEN <strong>and</strong> STRIDE combinations.<br />

For double-precision vector instructions, some of the permitted LEN <strong>and</strong> STRIDE combinations would<br />

cause the same register to appear twice in a vector. If a double-precision vector instruction is executed with<br />

such a LEN <strong>and</strong> STRIDE combination in effect, the instruction is UNPREDICTABLE. The last column of Table<br />

2-2 indicates which LEN <strong>and</strong> STRIDE combinations this applies to. Double-precision scalar instructions<br />

work normally with all of the permitted LEN <strong>and</strong> STRIDE combinations.<br />

Table F-1 Vector length <strong>and</strong> stride combinations<br />

LEN STRIDE Vector length Vector stride Double-precision vector instructions<br />

0b000 0b00 1 - All instructions are scalar<br />

0b001 0b00 2 1 Work as described in this appendix<br />

0b001 0b11 2 2 Work as described in this appendix<br />

0b010 0b00 3 1 Work as described in this appendix<br />

0b010 0b11 3 2 UNPREDICTABLE<br />

0b011 0b00 4 1 Work as described in this appendix<br />

0b011 0b11 4 2 UNPREDICTABLE<br />

0b100 0b00 5 1 UNPREDICTABLE<br />

<strong>ARM</strong> DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. AppxF-3

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!