ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
Note
This condition is consistent with the maintenance required for a Virtually Indexed Physically Tagged (VIPT)
instruction cache.
Software can read the Cache Type Register to determine whether the IVIPT extension is implemented, see
c0, Cache Type Register (CTR) on page B3-83.
Functionally, the relationship between cache type and the software management requirement depends on
whether the operating system uses ASIDs to distinguish processes that use different translation tables:
when ASIDs are used, management is similar for a VIPT and an ASID-tagged VIVT cache
when ASIDs are not used, management is similar for a VIVT and an ASID-tagged VIVT cache.
A remapping policy that supports ASID changes means that translation tables can be swapped simply by
updates to the TTBR0, TTBR1 and TTBCR registers, with an appropriate change of the ASID held in the
CONTEXTIDR, see Synchronization of changes of ASID and TTBR on page B3-60. Such changes are
transparent to an ASID-tagged VIVT instruction cache until an ASID value is reused. In contrast, a VIVT
instruction cache that is not ASID-tagged must be invalidated whenever the virtual to physical address
mappings change. Therefore, such a cache must be invalidated on an ASID change.
Software written to rely on a VIPT instruction cache must only be used with processors that implement the
IVIPT. For maximum compatibility across processors, ARM recommends that operating systems target the
ARMv7 base architecture that uses ASID-tagged VIVT instruction caches, and do not assume the presence
of the IVIPT extension. Software that relies on the IVIPT extension might fail in an UNPREDICTABLE way
on an ARMv7 implementation that does not include the IVIPT extension.
With an instruction cache, the distinction between a VIPT cache and a PIPT cache is much less visible to
the programmer than it is for a data cache, because normally the contents of an instruction cache are not
changed by writing to the cached memory. However, there are situations where a program must distinguish
between the different cache tagging strategies. Example B3-1 describes such a situation.
Example B3-1 A situation where software must be aware of the
Instruction cache tagging strategy
Two processes, P1 and P2, share some code and have separate virtual mappings to the same region of
instruction memory. P1 changes this region, for example as a result of a JIT, or some other self-modifying
code operation. P2 needs to see the modified code.
As part of its self-modifying code operation, P1 must invalidate the changed locations from the instruction
cache. For more information, see Ordering of cache and branch predictor maintenance operations on
page B2-21. If this invalidation is performed by MVA, and the instruction cache is a VIPT cache, then P2
might continue to see the old code.
In this situation, if the instruction cache is a VIPT cache, after the code modification the entire instruction
cache must be invalidated to ensure P2 observes the new version of the code.
B3-24 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B