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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Application Level Programmers’ Model<br />

Use of H<strong>and</strong>lerBase<br />

ThumbEE h<strong>and</strong>lers are entered by reference to a H<strong>and</strong>lerBase address, defined by the TEEHBR. See<br />

ThumbEE H<strong>and</strong>ler Base Register (TEEHBR) on page A2-71. Table A2-13 shows how the h<strong>and</strong>lers are<br />

arranged in relation to the value of H<strong>and</strong>lerBase:<br />

The IndexCheck occurs when a CHKA instruction detects an index out of range. For more information, see<br />

CHKA on page A9-15.<br />

The NullCheck occurs when any memory access instruction is executed with a value of 0 in the base register.<br />

For more information, see Null checking on page A9-3.<br />

Note<br />

Offset from H<strong>and</strong>lerBase Name Value stored<br />

Table A2-13 Access to ThumbEE h<strong>and</strong>lers<br />

-0x0008 IndexCheck Branch to IndexCheck h<strong>and</strong>ler<br />

-0x0004 NullCheck Branch to NullCheck h<strong>and</strong>ler<br />

+0x0000 H<strong>and</strong>ler_00 Implementation of H<strong>and</strong>ler_00<br />

+0x0020 H<strong>and</strong>ler_01 Implementation of H<strong>and</strong>ler_01<br />

... ... ...<br />

+(0x0000 + 32n) H<strong>and</strong>ler_ Implementation of H<strong>and</strong>ler_<br />

... ... Implementation of additional h<strong>and</strong>lers<br />

Checks are similar to conditional branches, with the added property that they clear the IT bits when taken.<br />

Other h<strong>and</strong>lers are called using explicit h<strong>and</strong>ler call instructions. For details see the following sections:<br />

HB, HBL on page A9-16<br />

HBLP on page A9-17<br />

HBP on page A9-18.<br />

A2-72 Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. <strong>ARM</strong> DDI 0406B

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