ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
B3.13.5 TLB operations
The TLBRecord type represents the contentsof a TLB entry:
// Types of TLB entry
enumeration TLBRecType = { TLBRecType_SmallPage,
TLBRecType_LargePage,
TLBRecType_Section,
TLBRecType_Supersection,
TLBRecType_MMUDisabled
};
type TLBRecord is (
Permissions perms,
bit nG, // ‘0’ = Global, ‘1’ = not Global
bits(4) domain,
boolean sectionnotpage,
TLBRecType type,
AddressDescriptor addrdesc
)
The CheckTLB() function checks whether the TLB contains an entry that matches an ASID and address, and
returns TRUE and the matching TLBRecord if so. Otherwise, it returns FALSE and an UNKNOWN TLBRecord.
(boolean, TLBRecord) CheckTLB(bits(8) asid, bits(32) address)
The AssignToTLB() procedure supplies an ASID and new TLBRecord to the TLB, for possible allocation to a
TLB entry. It is IMPLEMENTATION DEFINED under what circumstances this allocation takes place, and TLB
entries might also be allocated at other times.
AssignToTLB(bits(8) asid, bits(32) mva, TLBRecord entry)
B3.13.6 Translation table walk
The following pseudocode describes the translation table walk operation:
// TranslationTableWalk()
// ======================
//
// Returns a result of a translation table walk in TLBRecord form.
TLBRecord TranslationTableWalk(bits(32) mva, boolean is_write)
TLBRecord result;
AddressDescriptor l1descaddr;
AddressDescriptor l2descaddr;
if SCTLR.M == ‘1’ then // MMU is enabled
domain = bits(4) UNKNOWN; // For Data Abort exceptions found before a domain is known
// Determine correct Translation Table Base Register to use.
n = UInt(TTBCR.N);
B3-158 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B