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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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System Instructions<br />

B6.1.11 STM (user registers)<br />

Store Multiple (user registers) is UNPREDICTABLE in User or System modes. In exception modes, it stores<br />

multiple User mode registers to consecutive memory locations using an address from a banked base register.<br />

Writeback to the base register is not available with this instruction.<br />

Encoding A1 <strong>ARM</strong>v4*, <strong>ARM</strong>v5T*, <strong>ARM</strong>v6*, <strong>ARM</strong>v7<br />

STM{amode} ,^<br />

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

cond 1 0 0 P U 1 (0) 0 Rn register_list<br />

n = UInt(Rn); registers = register_list; increment = (U == ‘1’); wordhigher = (P == U);<br />

if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;<br />

Assembler syntax<br />

STM{amode} , ^<br />

where:<br />

See St<strong>and</strong>ard assembler syntax fields on page A8-7.<br />

amode is one of:<br />

DA Decrement After. The consecutive memory addresses end at the address in the<br />

base register. For this instruction, ED, meaning Empty Descending, is equivalent<br />

to DA. Encoded as P = 0, U = 0.<br />

DB Decrement Before. The consecutive memory addresses end one word below the<br />

address in the base register. For this instruction, FD, meaning Full Descending,<br />

is equivalent to DB. Encoded as P = 1, U = 0.<br />

IA Increment After. The consecutive memory addresses start at the address in the<br />

base register. This is the default, <strong>and</strong> is normally omitted. For this instruction,<br />

EA, meaning Empty Ascending, is equivalent to IA. Encoded as P = 0, U = 1.<br />

IB Increment Before. The consecutive memory addresses start one word above the<br />

address in the base register. For this instruction, FA, meaning Full Ascending, is<br />

equivalent to IB. Encoded as P = 1, U = 1.<br />

The base register. This register can be the SP.<br />

Is a list of one or more registers, separated by commas <strong>and</strong> surrounded by { <strong>and</strong> }. It<br />

specifies the set of registers to be stored by the STM instruction. The registers are stored with<br />

the lowest-numbered register to the lowest memory address, through to the<br />

highest-numbered register to the highest memory address.<br />

The pre-UAL syntax STM{amode} is equivalent to STM{amode}.<br />

B6-22 Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. <strong>ARM</strong> DDI 0406B

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