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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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The CPUID Identification Scheme<br />

0b0010 As for 0b0001, <strong>and</strong> adds:<br />

Clean <strong>and</strong> invalidate cache line by set/way.<br />

0b0011 As for 0b0010, <strong>and</strong> adds:<br />

Invalidate cache line by set/way.<br />

If this field is set to a value other than 0b0000 then the L1 Harvard cache s/w field,<br />

bits [11:8], must be set to 0b0000.<br />

L1 Harvard cache s/w, bits [11:8]<br />

Indicates the supported Level 1 cache line maintenance operations by set/way, for a Harvard<br />

cache implementation. Permitted values are:<br />

0b0000 None supported. This is the required setting for <strong>ARM</strong>v7, because <strong>ARM</strong>v7<br />

requires a hierarchical cache implementation.<br />

0b0001 Supported Level 1 Harvard cache line maintenance operations by set/way are:<br />

Clean data cache line by set/way<br />

Clean <strong>and</strong> invalidate data cache line by set/way.<br />

0b0010 As for 0b0001, <strong>and</strong> adds:<br />

Invalidate data cache line by set/way.<br />

0b0011 As for 0b0010, <strong>and</strong> adds:<br />

Invalidate instruction cache line by set/way.<br />

If this field is set to a value other than 0b0000 then the L1 unified cache s/w field,<br />

bits [15:12], must be set to 0b0000.<br />

L1 unified cache VA, bits [7:4]<br />

Indicates the supported Level 1 cache line maintenance operations by MVA, for a unified<br />

cache implementation. Permitted values are:<br />

0b0000 None supported. This is the required setting for <strong>ARM</strong>v7, because <strong>ARM</strong>v7<br />

requires a hierarchical cache implementation.<br />

0b0001 Supported Level 1 unified cache line maintenance operations by MVA are:<br />

Clean cache line by MVA<br />

Invalidate cache line by MVA<br />

Clean <strong>and</strong> invalidate cache line by MVA.<br />

0b0010 As for 0b0001, <strong>and</strong> adds:<br />

Invalidate branch predictor by MVA, if branch predictor is implemented.<br />

If this field is set to a value other than 0b0000 then the L1 Harvard cache VA field, bits [3:0],<br />

must be set to 0b0000.<br />

L1 Harvard cache VA, bits [3:0]<br />

Indicates the supported Level 1 cache line maintenance operations by MVA, for a Harvard<br />

cache implementation. Permitted values are:<br />

0b0000 None supported. This is the required setting for <strong>ARM</strong>v7, because <strong>ARM</strong>v7<br />

requires a hierarchical cache implementation.<br />

<strong>ARM</strong> DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. B5-13

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