ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.279 VBIF, VBIT, VBSL
VBIF (Vector Bitwise Insert if False), VBIT (Vector Bitwise Insert if True), and VBSL (Vector Bitwise Select)
perform bitwise selection under the control of a mask, and place the results in the destination register. The
registers can be either quadword or doubleword, and must all be the same size.
Encoding T1 / A1 Advanced SIMD
V , ,
V , ,
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1 0 D op Vn Vd 0 0 0 1 N Q M 1 Vm
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 1 0 D op Vn Vd 0 0 0 1 N Q M 1 Vm
if Q == ‘1’ && (Vd == ‘1’ || Vn == ‘1’ || Vm == ‘1’) then UNDEFINED;
if op == ‘00’ then SEE VEOR;
if op == ‘01’ then operation = VBitOps_VBSL;
if op == ‘10’ then operation = VBitOps_VBIT;
if op == ‘11’ then operation = VBitOps_VBIF;
d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm); regs = if Q == ‘0’ then 1 else 2;
A8-550 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B