ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
About the TLB maintenance operations
For more information about TLBs and their maintenance see Translation Lookaside Buffers (TLBs) on
page B3-54, and in particular TLB maintenance on page B3-56. The following subsections give more
information about the TLB maintenance operations:
Invalidate entire TLB
Invalidate single TLB entry by MVA
Invalidate TLB entries by ASID match
Invalidate TLB entries by MVA all ASID on page B3-141.
As stated in the footnotes to Table B3-35 on page B3-139:
If an Instruction TLB or Data TLB operation is used on a system that implements a Unified TLB then
the operation is performed on the Unified TLB
If a Unified TLB operation is used on a system that implements separate Instruction and Data TLBs
then the operation is performed on both the Instruction TLB and the Data TLB.
The mnemonics for the operations to invalidate a unified TLB that are defined in the ARM v7 base
architecture were previously UTLBIALL, UTLBIMV, and UTLBIASID. These remain synonyms for
these operations, but ARM deprecates the use of the older names. These are the operations with
CRm==c7, opc2=={0,1,2}.
For information about the synchronization of the TLB maintenance operations see TLB maintenance
operations and the memory order model on page B3-59.
Invalidate entire TLB
The Invalidate entire TLB operations invalidate all unlocked entries in the TLB. The value in the register Rt
specified by the MCR instruction used to perform the operation is ignored. You do not have to write a value
to the register before issuing the MCR instruction.
Invalidate single TLB entry by MVA
The Invalidate Single Entry operations invalidate a TLB entry that matches the MVA and ASID values
provided as an argument to the operation. The register format required is:
31 12 11 8 7 0
MVA SBZ ASID
With global entries in the TLB, the supplied ASID value is not checked.
Invalidate TLB entries by ASID match
The Invalidate on ASID Match operations invalidate all TLB entries for non-global pages that match the
ASID value provided as an argument to the operation. The register format required is:
31 8 7 0
SBZ ASID
B3-140 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B