ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Note
Common VFP Subarchitecture Specification
An Underflow trapped exception can occur only when FPSCR.FZ is 0, because
when FPSCR.FZ is 1, FPSCR.UFE is ignored and treated as 0.
In both cases this bit must be cleared to 0 by the exception handling routine.
OFF, bit [2] Overflow trapped exception flag, or IMPLEMENTATION DEFINED. The meaning of this bit
depends on the value of FPEXC.TFV:
FPEXC.TFV == 0
This bit is IMPLEMENTATION DEFINED. It can contain IMPLEMENTATION DEFINED
information about the cause of an exception. It might be used by the
implementation to indicate why an instruction was bounced to support code.
FPEXC.TFV == 1
This bit is the Overflow trapped exception flag. It indicates whether an
Overflow exception occurred while FPSCR.OFE was 1.
In this case, the meaning of this bit is:
0 Overflow exception has not occurred.
1 Overflow exception has occurred.
In both cases this bit must be cleared to 0 by the exception handling routine.
DZF, bit [1] Divide-by-zero trapped exception flag, or IMPLEMENTATION DEFINED. The meaning of this
bit depends on the value of FPEXC.TFV:
FPEXC.TFV == 0
This bit is IMPLEMENTATION DEFINED. It can contain IMPLEMENTATION DEFINED
information about the cause of an exception. It might be used by the
implementation to indicate why an instruction was bounced to support code.
FPEXC.TFV == 1
This bit is the Divide-by-zero trapped exception flag. It indicates whether a
Divide-by-zero exception occurred while FPSCR.DZE was 1.
In this case, the meaning of this bit is:
0 Divide-by-zero exception has not occurred.
1 Divide-by-zero exception has occurred.
In both cases this bit must be cleared to 0 by the exception handling routine.
IOF, bit [0] Invalid Operation trapped exception flag, or IMPLEMENTATION DEFINED. The meaning of
this bit depends on the value of FPEXC.TFV:
FPEXC.TFV == 0
This bit is IMPLEMENTATION DEFINED. It can contain IMPLEMENTATION DEFINED
information about the cause of an exception. It might be used by the
implementation to indicate why an instruction was bounced to support code.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. AppxB-19