ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

B2.2 Caches
Common Memory System Architecture Features
The concept of caches is described in Caches and memory hierarchy on page A3-51. This section describes
the cache identification and control mechanisms in ARMv7. These are described in the following sections:
Cache identification
Cache behavior on page B2-5
Cache enabling and disabling on page B2-8
Cache maintenance functionality on page B2-9
The interaction of cache lockdown with cache maintenance on page B2-18
Branch predictors on page B2-19
Ordering of cache and branch predictor maintenance operations on page B2-21
Multiprocessor effects on cache maintenance operations on page B2-23
System-level caches on page B2-26.
Note
The cache identification and control mechanisms for previous versions of the ARM architecture are
described in:
Cache support on page AppxG-21, for ARMv6
Cache support on page AppxH-21, for the ARMv4 and ARMv5 architectures.
B2.2.1 Cache identification
The ARMv7 cache identification consists of a set of registers that describe the implemented caches that are
under the control of the processor:
A single Cache Type Register defines:
— the minimum line length of any of the instruction caches
— the minimum line length of any of the data or unified caches
— the cache indexing and tagging policy of the Level 1 instruction cache.
For more information, see:
— c0, Cache Type Register (CTR) on page B3-83, for a VMSA implementation
— c0, Cache Type Register (CTR) on page B4-34, for a PMSA implementation.
A single Cache Level ID Register defines:
— the type of cache implemented at a each cache level, up to the maximum of seven levels
— the Level of Coherence for the caches
— the Level of Unification for the caches.
For more information, see:
— c0, Cache Level ID Register (CLIDR) on page B3-92, for a VMSA implementation
— c0, Cache Level ID Register (CLIDR) on page B4-41, for a PMSA implementation.
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